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CD40182 PDF预览

CD40182

更新时间: 2024-11-28 22:56:43
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
9页 143K
描述
CMOS Look-Ahead Carry Generator

CD40182 数据手册

 浏览型号CD40182的Datasheet PDF文件第2页浏览型号CD40182的Datasheet PDF文件第3页浏览型号CD40182的Datasheet PDF文件第4页浏览型号CD40182的Datasheet PDF文件第5页浏览型号CD40182的Datasheet PDF文件第6页浏览型号CD40182的Datasheet PDF文件第7页 
CD40182BMS  
CMOS Look-Ahead Carry Generator  
December 1992  
Features  
Description  
• High Voltage Type (20V Rating)  
The CD40182BMS is a high-speed look-ahead carry gener-  
ator capable of anticipating a carry across four binary adders  
or groups of adders. The CD40182BMS is cascadable to  
perform full look-ahead across n-bit adders. Carry, propa-  
gate-carry, and generate-carry functions are provided as  
enumerated in the terminal designation below.  
• Generates High-Speed Carry Across Four Adders or  
Adder Groups  
• High-Speed Operation  
- tPHL, tPLH =100 ns (typ) at VDD = 10V  
The CD40182BMS, when used in conjuction with the  
CD40181BMS arithmetic logic unit (ALU), provides full high-  
speed look-ahead carry capability for up to n-bit words. Each  
CD40182BMS generates the look-ahead (anticipated carry)  
• Cascadable for Fast Carries Over N Bits  
• Designed for Use with CD40181BMS ALU  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
across  
a
group of four ALU’s. In addition, other  
CD40182BMS’s may be employed to anticipate the carry  
across sections of four look-ahead blocks up to n-bits. Carry  
inputs and outputs of the CD40181BMS are active-high  
• Standardized Symmetrical Output Characteristics  
• Maximum Input Current of 1µA at 18V Over Full Pack- logic, and carry-generate (G) and carry-propagate (P) out-  
age Temperature Range; 100nA at 18V and +25oC  
puts are active-low. Therefore the inputs and outputs of the  
CD40182BMS are compatible.  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
The CD40182BMS is supplied in these 16-lead outline  
packages:  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
H4V  
H1E  
H6P  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
The CD40182BMS is similar to industry type MC14582.  
Applications  
• High-Speed Parallel Arithmetric Units  
• Multi-Level Look-Ahead Carry Generation for Long  
Word Lengths  
Pinout  
Functional Diagram  
CD40182BMS  
TOP VIEW  
3
G0  
1
G1  
14  
5
G
P
G1  
P1  
1
2
3
4
5
6
7
8
16 VDD  
15 P2  
G2  
G3  
12  
11  
9
Cn + x  
Cn + y  
Cn + z  
G0  
P0  
14 G2  
4
2
P0  
P1  
P2  
P3  
13 Cn  
15  
6
G3  
P3  
12 Cn + x  
11 Cn + y  
10 G  
7
P
P
VDD = 16  
VSS = 8  
Cn 13  
10  
G
9
Cn + z  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3362  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1410  

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