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CD40163BMN PDF预览

CD40163BMN

更新时间: 2024-11-13 23:40:23
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 153K
描述
Synchronous Up Counter

CD40163BMN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.89
其他特性:TCO OUTPUT计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
传播延迟(tpd):400 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Counters
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:7 MHz

CD40163BMN 数据手册

 浏览型号CD40163BMN的Datasheet PDF文件第2页浏览型号CD40163BMN的Datasheet PDF文件第3页浏览型号CD40163BMN的Datasheet PDF文件第4页浏览型号CD40163BMN的Datasheet PDF文件第5页浏览型号CD40163BMN的Datasheet PDF文件第6页浏览型号CD40163BMN的Datasheet PDF文件第7页 
March 1988  
CD40160BM/CD40160BC  
Decade Counter with Asynchronous Clear  
CD40161BM/CD40161BC  
Binary Counter with Asynchronous Clear  
CD40162BM/CD40162BC  
Decade Counter with Synchronous Clear  
CD40163BM/CD40163BC  
Binary Counter with Synchronous Clear  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
These (synchronous presettable up) counters are monolith-  
ic complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode transis-  
tors. They feature an internal carry look-ahead for fast  
counting schemes and for cascading packages without ad-  
ditional gating.  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
fan out of 2 driving 74L  
or 1 driving 74LS  
Y
Internal look-ahead for fast counting schemes  
Carry output for N-bit cascading  
Load control line  
Y
Y
Y
Y
A low level at the load input disables counting and causes  
the outputs to agree with the data input after the next posi-  
tive clock edge. The clear function for the CD40162B and  
CD40163B is synchronous and a low level at the clear input  
sets all four outputs low after the next positive clock edge.  
The clear function for the CD40160B and CD40161B is  
asynchronous and a low level at the clear input sets all four  
outputs low, regardless of the state of the clock.  
Synchronously programmable  
Equivalent to MC14160B, MC14161B, MC14162B,  
MC14163B  
Y
Equivalent to MM74C160, MM74C161, MM74C162,  
MM74C163  
Counting is enabled when both count enable inputs are  
high. Input T is fed forward to also enable the carry out. The  
carry output is a positive pulse with a duration approximately  
equal to the positive portion of Q and can be used to en-  
A
able successive cascaded stages. Logic transitions at the  
enable P or T inputs can occur when the clock is high or  
low.  
Connection Diagram  
Dual-In-Line Package  
Order Number CD40160B, CD40161B,  
CD40162B or CD40163B  
TL/F/5986–1  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5986  
RRD-B30M105/Printed in U. S. A.  

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