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CBTL02042BBQ PDF预览

CBTL02042BBQ

更新时间： 2024-11-16 09:16:19
品牌 Logo 应用领域
恩智浦 - NXP 解复用器开关逻辑集成电路PC
页数 文件大小 规格书
16页 317K
描述
3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen2

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CBTL02042BBQ 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：2.5X4.5 MM, 0.85MM, PLASTIC, MO-241, DHQFN-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.7
Is Samacsys：NJESD-30 代码：R-PQCC-N20
逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER湿度敏感等级：1
端子数量：20封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260认证状态：Not Qualified
表面贴装：YES端子形式：NO LEAD
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

CBTL02042BBQ 数据手册

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CBTL02042A; CBTL02042B  
3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer  
switch for PCI Express Gen2  
Rev. 1 — 10 March 2011  
Product data sheet  
1. General description  
CBTL02042A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI  
Express Generation 2 (Gen2), and other high-speed serial interface applications. The  
CBTL02042A/B can switch two differential signals to one of two locations. Using a unique  
design technique, NXP has minimized the impedance of the switch such that the  
attenuation observed through the switch is negligible, and also minimized the  
channel-to-channel skew as well as channel-to-channel crosstalk, as required by the  
high-speed serial interface. CBTL02042A/B allows expansion of existing high speed ports  
for extremely low power.  
The device's pinouts are optimized to match different application layouts. CBTL02042A  
has input and output pins on the opposite of the package, and is suitable for edge  
connector(s) with different signal sources on the motherboard. CBTL02042B has outputs  
on both sides of the package, and the device can be placed between two connectors to  
multiplex differential signals from a controller. Please refer to Section 8 for layout  
examples.  
2. Features and benefits  
„ 2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer  
„ High-speed signal switching for PCIe Gen2 5 Gbit/s  
„ High bandwidth: 7 GHz at −3 dB  
„ Low insertion loss:  
‹ −0.5 dB at 100 MHz  
‹ −1.2 dB at 2.5 GHz  
„ Low intra-pair skew: 5 ps typical  
„ Low inter-pair skew: 35 ps maximum  
„ Low crosstalk: −30 dB at 2.5 GHz  
„ Low off-state isolation: −25 dB at 2.5 GHz  
„ Low return loss: −20 dB at 2.5 GHz  
„ VDD operating range: 3.3 V ± 10 %  
„ Shutdown pin (XSD) for power-saving mode  
‹ Standby current less than 1 μA  
„ ESD tolerance:  
‹ 8 kV HBM  
‹ 1 kV CDM  
„ DHVQFN20 package  
1234567...16

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