5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 并行 IO 端口> CAT9555WI-T1
CAT9555WI-T1 PDF预览

CAT9555WI-T1

更新时间： 2024-02-28 13:18:13
品牌 Logo 应用领域
安森美 - ONSEMI 并行IO端口微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
17页 190K
描述
16-bit I²C and SMBus I/O Port with Interrupt

阅读下载

获取价格

CAT9555WI-T1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.19
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/229596.1.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=229596
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=2295963D View：https://componentsearchengine.com/viewer/3D.php?partID=229596
Samacsys PartID：229596Samacsys Image：https://componentsearchengine.com/Images/9/CAT9555WI-T1.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/CAT9555WI-T1.jpgSamacsys Pin Count：24
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：SOIC-24 CASE751BKSamacsys Released Date：2015-10-27 14:32:43
Is Samacsys：NJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：15.3 mm
湿度敏感等级：3位数：16
I/O 线路数量：16端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/5 V
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Parallel IO Port最大供电电压：5.5 V
最小供电电压：2.3 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.47 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

CAT9555WI-T1 数据手册

 浏览型号CAT9555WI-T1的Datasheet PDF文件第7页浏览型号CAT9555WI-T1的Datasheet PDF文件第8页浏览型号CAT9555WI-T1的Datasheet PDF文件第9页浏览型号CAT9555WI-T1的Datasheet PDF文件第11页浏览型号CAT9555WI-T1的Datasheet PDF文件第12页浏览型号CAT9555WI-T1的Datasheet PDF文件第13页 
CAT9555  
The command byte is the first byte to follow the device  
address byte during a write/read bus transaction. The  
register command byte acts as a pointer to determine  
which register will be written or read.  
ACKNOWLEDGE  
After a successful data transfer, each receiving device  
is required to generate an acknowledge. The  
acknowledging device pulls down the SDA line during  
the ninth clock cycle, signaling that it received the 8  
bits of data. The SDA line remains stable LOW during  
the HIGH period of the acknowledge related clock  
pulse (Figure 7).  
The input port register is a read only port. It reflects  
the incoming logic levels of the I/O pins, regardless of  
whether the pin is defined as an input or an output by  
the configuration register. Writes to the input port  
register are ignored.  
The CAT9555 responds with an acknowledge after  
receiving a START condition and its slave address. If  
the device has been selected along with a write  
operation, it responds with an acknowledge after  
receiving each data byte.  
Table 2. Registers 0 and 1 – Input Port Registers  
bit  
I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0  
default  
bit  
X
X
X
X
X
X
X
X
I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0  
When the CAT9555 begins a READ mode it transmits  
8 bits of data, releases the SDA line, and monitors the  
line for an acknowledge. Once it receives this  
acknowledge, the CAT9555 will continue to transmit  
data. If no acknowledge is sent by the Master, the  
device terminates data transmission and waits for a  
STOP condition. The master must then issue a stop  
condition to return the CAT9555 to the standby power  
mode and place the device in a known state.  
default  
X
X
X
X
X
X
X
X
Table 3. Registers 2 and 3 – Output Port Registers  
bit  
O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0  
default  
bit  
1
1
1
1
1
1
1
1
O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0  
default  
1
1
1
1
1
1
1
1
REGISTERS AND BUS TRANSACTIONS  
Table 4. Registers 4 and 5 – Polarity Inversion  
Registers  
The CAT9555 internal registers and their address and  
function are shown in Table 1.  
bit  
N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0  
Table 1. Register Command Byte  
Command (hex) Register  
default  
bit  
0
0
0
0
0
0
0
0
N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
Input Port 0  
default  
0
0
0
0
0
0
0
0
Input Port 1  
Output Port 0  
Table 5. Registers 6 and 7 – Configuration  
Registers  
Output Port 1  
bit  
C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0  
Polarity Inversion Port 0  
Polarity Inversion Port 1  
Configuration Port 0  
Configuration Port 1  
default  
bit  
1
1
1
1
1
1
1
1
C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0  
default  
1
1
1
1
1
1
1
1
BUS RELEASE DELAY (TRANSMITTER)  
BUS RELEASE DELAY (RECEIVER)  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
ACK SETUP (≥ t  
)
SU:DAT  
START  
ACK DELAY (≤ t  
)
AA  
Figure 7. Acknowledge Timing  
Doc. No. MD-9003 Rev. I  
10  
© 2008 SCILLC. All rights reserved  
Characteristics subject to change without notice  
1...78910111213...17

下载PDF

与CAT9555WI-T1相关器件

型号 品牌 描述 获取价格 数据表
CAT9555WI-T2 CATALYST 16-bit I2C and SMBus I/O Port with Interrupt

获取价格
CAT9555YI CATALYST 16-bit I2C and SMBus I/O Port with Interrupt

获取价格
CAT9555YI ONSEMI 16-bit I²C and SMBus I/O Port with Interrupt

获取价格
CAT9555YI-T1 CATALYST 16-bit I2C and SMBus I/O Port with Interrupt

获取价格
CAT9555YI-T2 ONSEMI 16-bit I²C and SMBus I/O Port with Interrupt

获取价格
CAT9555YI-T2 CATALYST 16-bit I2C and SMBus I/O Port with Interrupt

获取价格

与CAT9555WI-T1相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证