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CAT93C56SE-1.8REV-E PDF预览

CAT93C56SE-1.8REV-E

更新时间: 2024-11-21 19:28:43
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
9页 407K
描述
EEPROM, 128KX16, Serial, CMOS, PDSO8, SOIC-8

CAT93C56SE-1.8REV-E 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownECCN代码:3A991.B.1.B.1
HTS代码:8542.32.00.51风险等级:5.04
备用内存宽度:8最大时钟频率 (fCLK):0.25 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm内存密度:2097152 bit
内存集成电路类型:EEPROM内存宽度:16
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:4.57 mm
串行总线类型:MICROWIRE最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:TIN LEAD
端子形式:GULL WING端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

CAT93C56SE-1.8REV-E 数据手册

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E
CAT93C56/57 (Die Rev. E)  
2K-Bit Microwire Serial EEPROM  
TM  
FEATURES  
High speed operation: 1MHz  
Power-up inadvertant write protection  
1,000,000 Program/erase cycles  
100 year data retention  
Low power CMOS technology  
1.8 to 6.0 volt operation  
Selectable x8 or x16 memory organization  
Self-timed write cycle with auto-clear  
Hardware and software write protection  
Commercial, industrial and automotive  
temperature ranges  
Sequential read  
“Green” package option available  
DESCRIPTION  
using Catalyst’s advanced CMOS EEPROM floating  
gate technology. The devices are designed to endure  
1,000,000 program/erase cycles and has a data reten-  
tion of 100 years. The devices are available in 8-pin DIP,  
SOIC, TSSOP and 8-pad TDFN packages.  
The CAT93C56/57 are 2K-bit Serial EEPROM memory  
devices which are configured as either registers of 16  
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each  
register can be written (or read) serially by using the  
DI (or DO) pin. The CAT93C56/57 are manufactured  
PIN CONFIGURATION  
FUNCTIONAL SYMBOL  
VCC  
SOIC Package (J,W)  
DIP Package (P, L)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
NC  
CC  
ORG  
CS  
DI  
NC  
V
CC  
CS  
ORG  
GND  
DO  
DO  
SK  
DI  
SK  
NC  
SOIC Package (S,V)  
SOIC Package (K,X)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC  
ORG  
GND  
CC  
GND  
NC  
ORG  
GND  
PIN FUNCTIONS  
DO  
DO  
Pin Name  
Function  
Chip Select  
Clock Input  
CS  
TSSOP Package (U,Y)  
SK  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
DI  
Serial Data Input  
Serial Data Output  
+1.8 to 6.0V Power Supply  
Ground  
NC  
DO  
VCC  
GND  
ORG  
NC  
ORG  
GND  
DO  
TDFN Package (RD4, ZD4)  
Memory Organization  
No Connection  
V
CC  
NC  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
Note: When the ORG pin is connected to VCC, the x16 organiza-  
tion is selected. When it is connected to ground, the x8 pin is  
selected. If the ORG pin is left unconnected, then an internal pullup  
device will select the x16 organization.  
ORG  
GND  
DO  
Bottom View  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice.  
Doc. No. 1088, Rev. N  

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