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CAT93C56LI-1.8 PDF预览

CAT93C56LI-1.8

更新时间: 2024-11-23 19:49:31
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
10页 80K
描述
EEPROM, 128X16, Serial, CMOS, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8

CAT93C56LI-1.8 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:DIP包装说明:DIP, DIP8,.3
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.41其他特性:1000000 PROGRAM/ERASE CYCLES; 100 YEAR DATA RETENTION
备用内存宽度:8最大时钟频率 (fCLK):0.25 MHz
数据保留时间-最小值:100耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PDIP-T8JESD-609代码:e3
长度:9.36 mm内存密度:2048 bit
内存集成电路类型:EEPROM内存宽度:16
功能数量:1端子数量:8
字数:128 words字数代码:128
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128X16
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:2/5 V
认证状态:Not Qualified座面最大高度:4.57 mm
串行总线类型:MICROWIRE最大待机电流:0.00001 A
子类别:EEPROMs最大压摆率:0.003 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
写保护:SOFTWAREBase Number Matches:1

CAT93C56LI-1.8 数据手册

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E
CAT93C46/56/57/66/86  
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM  
TM  
FEATURES  
High speed operation:  
Power-up inadvertant write protection  
1,000,000 Program/erase cycles  
100 year data retention  
– 93C46/56/57/66: 1MHz  
– 93C86: 3MHz  
Low power CMOS technology  
Commercial, industrial and automotive  
1.8 to 6.0 volt operation  
temperature ranges  
Selectable x8 or x16 memory organization  
Self-timed write cycle with auto-clear  
Hardware and software write protection  
Sequential read (except CAT93C46)  
Program enable (PE) pin (CAT93C86 only)  
“Green” package option available  
DESCRIPTION  
CMOS EEPROM floating gate technology. The devices  
aredesignedtoendure1,000,000program/erasecycles  
and have a data retention of 100 years. The devices are  
available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-  
pad TDFN packages.  
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit  
Serial EEPROM memory devices which are configured  
as either registers of 16 bits (ORG pin at VCC) or 8 bits  
(ORGpinatGND). Eachregistercanbewritten(orread)  
serially by using the DI (or DO) pin. The CAT93C46/56/  
57/66/86 are manufactured using Catalyst’s advanced  
PIN CONFIGURATION  
TSSOP Package (U,Y)  
SOIC Package (J,W) SOIC Package (S,V)  
DIP Package (P, L)  
SOIC Package (K,X)  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
CS  
SK  
DI  
V
CS  
SK  
DI  
V
V
CC  
NC  
NC (PE*)  
CC  
CC  
CC  
NC (PE*)  
V
NC (PE*)  
ORG  
NC (PE*)  
ORG  
CC  
ORG  
CS  
ORG  
GND  
DO  
GND  
SK  
DI  
DO  
GND  
DO  
GND  
DO  
*Only For 93C86  
** TSSOP (U/Y) package only available for 93C46/56/57/66  
TDFN Package (RD4, ZD4)  
PIN FUNCTIONS  
BLOCK DIAGRAM  
V
CC  
NC  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
GND  
Pin Name  
Function  
Chip Select  
Clock Input  
CAT93C46  
CAT93C56  
CAT93C66  
CC  
ORG  
GND  
CS  
DO  
SK  
ADDRESS  
DECODER  
MEMORY ARRAY  
ORGANIZATION  
DI  
Serial Data Input  
Serial Data Output  
+1.8 to 6.0V Power Supply  
Ground  
ORG  
Bottom View  
DO  
VCC  
GND  
ORG  
NC  
DATA  
REGISTER  
Memory Organization  
No Connection  
OUTPUT  
BUFFER  
DI  
MODE DECODE  
LOGIC  
PE*  
Program Enable  
CS  
PE*  
Note: When the ORG pin is connected to VCC,  
the x16 organization is selected. When it is  
connected to ground, the x8 pin is selected. If  
the ORG pin is left unconnected, then an internal  
pullup device will select the x16 organization.  
CLOCK  
GENERATOR  
DO  
SK  
© 2003 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice.  
Doc. No. 1023, Rev. J  

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