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CAT93C46PI-1.8REVL PDF预览

CAT93C46PI-1.8REVL

更新时间： 2024-11-16 13:40:27
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
9页 584K
描述
EEPROM, 64X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8

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CAT93C46PI-1.8REVL 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.61
Is Samacsys：N备用内存宽度：8
最大时钟频率 (fCLK)：0.25 MHzJESD-30 代码：R-PDIP-T8
长度：9.59 mm内存密度：1024 bit
内存集成电路类型：EEPROM内存宽度：16
功能数量：1端子数量：8
字数：64 words字数代码：64
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64X16
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：SERIAL认证状态：Not Qualified
座面最大高度：4.57 mm串行总线类型：MICROWIRE
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：1.8 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

CAT93C46PI-1.8REVL 数据手册

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E
CAT93C46 (Die Rev. L)  
1K-Bit Microwire Serial EEPROM  
TM  
FEATURES  
ꢀ High speed operation: 1MHz  
ꢀ Power-up inadvertant write protection  
ꢀ 1,000,000 Program/erase cycles  
ꢀ 100 year data retention  
ꢀ Low power CMOS technology  
ꢀ 1.8 to 6.0 volt operation  
ꢀ Selectable x8 or x16 memory organization  
ꢀ Self-timed write cycle with auto-clear  
ꢀ Hardware and software write protection  
ꢀ Commercial, industrial and automotive  
temperature ranges  
ꢀ “Green” package option available  
DESCRIPTION  
Catalyst’s advanced CMOS EEPROM floating gate  
technology. Thedeviceisdesignedtoendure1,000,000  
program/erase cycles and has a data retention of 100  
years. The device is available in 8-pin DIP, 8-pin SOIC,  
8-pin TSSOP and 8-pad TDFN packages.  
The CAT93C46 is a 1K-bit Serial EEPROM memory  
device which is configured as either registers of 16 bits  
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each  
register can be written (or read) serially by using the  
DI (or DO) pin. The CAT93C46 is manufactured using  
PIN CONFIGURATION  
FUNCTIONAL SYMBOL  
VCC  
SOIC Package (J,W)  
DIP Package (P, L)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
NC  
CC  
ORG  
CS  
DI  
NC  
V
CC  
CS  
ORG  
GND  
DO  
DO  
SK  
DI  
SK  
NC  
SOIC Package (S,V)  
SOIC Package (K,X)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC  
ORG  
GND  
CC  
GND  
NC  
ORG  
GND  
PIN FUNCTIONS  
DO  
DO  
Pin Name  
Function  
Chip Select  
Clock Input  
CS  
TSSOP Package (U,Y)  
SK  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
DI  
Serial Data Input  
Serial Data Output  
+1.8 to 6.0V Power Supply  
Ground  
NC  
DO  
VCC  
GND  
ORG  
NC  
ORG  
GND  
DO  
TDFN Package (RD4, ZD4)  
Memory Organization  
No Connection  
V
CC  
NC  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
Note: When the ORG pin is connected to VCC, the x16 organiza-  
tion is selected. When it is connected to ground, the x8 pin is  
selected. If the ORG pin is left unconnected, then an internal pullup  
device will select the x16 organization.  
ORG  
GND  
DO  
Bottom View  
© 2004 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice.  
Doc. No. 1086, Rev. L  
1234567...9

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