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CAT28C64BT13I-12 PDF预览

CAT28C64BT13I-12

更新时间: 2024-11-23 22:08:59
品牌 Logo 应用领域
CATALYST 可编程只读存储器
页数 文件大小 规格书
12页 60K
描述
64K-Bit CMOS PARALLEL E2PROM

CAT28C64BT13I-12 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:TSOP包装说明:TSOP1, TSSOP28,.53,22
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.02最长访问时间:120 ns
命令用户界面:NO数据轮询:YES
耐久性:1000000 Write/Erase CyclesJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:11.8 mm
内存密度:65536 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:2
功能数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP28,.53,22封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE页面大小:32 words
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.0001 A子类别:EEPROMs
最大压摆率:0.03 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.55 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
切换位:YES宽度:8 mm
最长写入周期时间 (tWC):5 msBase Number Matches:1

CAT28C64BT13I-12 数据手册

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CAT28C64B  
64K-Bit CMOS PARALLEL E2PROM  
FEATURES  
Fast Read Access Times:  
Commercial, Industrial and Automotive  
– 120/150ns  
Temperature Ranges  
Low Power CMOS Dissipation:  
– Active: 25 mA Max.  
Automatic Page Write Operation:  
– 1 to 32 Bytes in 5ms  
– Standby: 100 µA Max.  
– Page Load Timer  
Simple Write Operation:  
End of Write Detection:  
– Toggle Bit  
– On-Chip Address and Data Latches  
– Self-Timed Write Cycle with Auto-Clear  
DATA Polling  
Fast Write Cycle Time:  
100,000 Program/Erase Cycles  
100 Year Data Retention  
– 5ms Max.  
CMOS and TTL Compatible I/O  
Hardware and Software Write Protection  
DESCRIPTION  
The CAT28C64B is manufactured using Catalyst’s ad-  
vancedCMOSfloatinggatetechnology. Itisdesignedto  
endure 100,000 program/erase cycles and has a data  
retentionof100years.ThedeviceisavailableinJEDEC-  
approved28-pinDIP,28-pinTSOP,28-pinSOIC,or,32-  
pin PLCC package .  
The CAT28C64B is a fast, low power, 5V-only CMOS  
Parallel E2PROM organized as 8K x 8-bits. It requires a  
simple interface for in-system programming. On-chip  
address and data latches, self-timed write cycle with  
auto-clear and VCC power up/down write protection  
eliminate additional timing and protection hardware.  
DATA Polling and Toggle status bits signal the start and  
end of the self-timed write cycle. Additionally, the  
CAT28C64B features hardware and software write pro-  
tection.  
BLOCK DIAGRAM  
8,192 x 8  
E2PROM  
ARRAY  
ROW  
DECODER  
ADDR. BUFFER  
A –A  
5
12  
& LATCHES  
INADVERTENT  
WRITE  
PROTECTION  
HIGH VOLTAGE  
GENERATOR  
32 BYTE PAGE  
REGISTER  
V
CC  
CE  
OE  
WE  
CONTROL  
LOGIC  
I/O BUFFERS  
DATA POLLING  
AND  
TIMER  
TOGGLE BIT  
I/O –I/O  
0
7
ADDR. BUFFER  
& LATCHES  
A –A  
COLUMN  
DECODER  
0
4
5094 FHD F02  
Doc. No. 25006-0A 2/98 P-1  
© 1999 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1

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