Datasheet > CAT25C17GVATE13

CAT25C17GVATE13

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	305K
描述
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM

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CAT25C17GVATE13 数据手册

CAT25C11/03/05/09/17

and the WPEN bit) and the block protected sections in

the memory array when the chip is hardware write

protected. Only the sections of the memory array that

are not block protected can be written. Hardware write

protection is disabled when either WP pin is high or the

WPEN bit is zero.

After the correct read instruction and address are sent,

the data stored in the memory at the selected address is

shifted out on the SO pin. The data stored in the memory

atthenextaddresscanbereadsequentiallybycontinuing

to provide clock pulses. The internal address pointer is

automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address is reached, the address counter rolls over to

0000hallowingthereadcycletobecontinuedindefinitely.

DEVICE OPERATION

Write Enable and Disable

The read operation is terminated by pulling the CS high.

Read sequece is illustrated in Figure 4. Reading status

of the status register are shifted out on the SO line. If a

non-volatile write is in progress, the RDSR instruction

returns a high on SO. When the non-volatile write cycle

is completed, the status register data is read out.

The CAT25C11/03/05/09/17 contains a write enable

latch. This latch must be set before any write operation.

The device powers up in a write disable state when V_cc

is applied. WREN instruction will enable writes (set the

latch) to the device. WRDI instruction will disable writes

(reset the latch) to the device. Disabling writes will

protect the device against inadvertent writes.

READ Sequence

WRITE Sequence

The part is selected by pulling CS low. The 8-bit read

instructionistransmittedtotheCAT25C11/03/05/09/17,

followed by the 16-bit address for 25C09/17 (only 10-bit

addresses are used for 25C09, 11-bit addresses are

used for 25C17. The rest of the bits are don't care bits)

and 8-bit address for 25C11/03/05 (for the 25C05, bit 3

of the read data instruction contains address A8).

The CAT25C11/03/05/09/17 powers up in a Write Dis-

able state. Prior to any write instructions, the WREN

instruction must be sent to CAT25C11/03/05/09/17.

The device goes into Write enable state by pulling the

CS low and then clocking the WREN instruction into

CAT25C11/03/05/09/17. The CS must be brought high

Figure 4. Read Instruction Timing

20 21 22 23 24 25 26 27 28 29 30

OPCODE

BYTE ADDRESS*

DATA OUT

HIGH IMPEDANCE

MSB

*Please check the Byte Address Table.

*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05.

Note: Dashed Line= mode (1, 1) – – – –

Characteristics subject to change without notice

Doc. No. 1017, Rev. L

1...4 5 678 9 10...12

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与CAT25C17GVATE13相关器件

型号	品牌	描述	获取价格	数据表
CAT25C17GVE	CATALYST	EEPROM, 2KX8, Serial, CMOS, PDSO8, ROHS COMPLIANT, SOIC-8	获取价格
CAT25C17GVE-1.8	YAGEO	General Purpose Inductor, 150uH, 10%, 1 Element, Ferrite-Core, SMD, CHIP, ROHS COMPLIANT	获取价格
CAT25C17GVE-1.8TE13	YAGEO	General Purpose Inductor, 180uH, 10%, 1 Element, Ferrite-Core, SMD, CHIP, ROHS COMPLIANT	获取价格
CAT25C17GVETE13	CATALYST	1K/2K/4K/8K/16K SPI Serial CMOS EEPROM	获取价格
CAT25C17GVITE13	CATALYST	1K/2K/4K/8K/16K SPI Serial CMOS EEPROM	获取价格
CAT25C17GYA	YAGEO	General Purpose Inductor, 22uH, 20%, 1 Element, Ferrite-Core, SMD, CHIP, ROHS COMPLIANT	获取价格

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