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CAT25C17GVATE13 PDF预览

CAT25C17GVATE13

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 305K
描述
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM

CAT25C17GVATE13 数据手册

 浏览型号CAT25C17GVATE13的Datasheet PDF文件第1页浏览型号CAT25C17GVATE13的Datasheet PDF文件第2页浏览型号CAT25C17GVATE13的Datasheet PDF文件第3页浏览型号CAT25C17GVATE13的Datasheet PDF文件第5页浏览型号CAT25C17GVATE13的Datasheet PDF文件第6页浏览型号CAT25C17GVATE13的Datasheet PDF文件第7页 
CAT25C11/03/05/09/17  
the operation to be performed.  
FUNCTIONAL DESCRIPTION  
The CAT25C11/03/05/09/17 supports the SPI bus data  
transmission protocol. The synchronous Serial Periph-  
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to  
interface directly with many of todays popular  
microcontrollers. The CAT25C11/03/05/09/17 contains  
an8-bitinstructionregister. (Theinstructionset andthe  
operation codes are detailed in the instruction set table)  
PIN DESCRIPTION  
SI: Serial Input  
SI is the serial data input pin. This pin is used to input all  
opcodes, byte addresses, and data to be written to the  
25C11/03/05/09/17.Input data is latched on the rising  
edge of the serial clock for SPI modes (0, 0 & 1, 1).  
After the device is selected with CS going low, the first  
byte will be received. The part is accessed via the SI pin,  
with data being clocked in on the rising edge of SCK.  
Thefirstbytecontainsoneofthesixop-codesthatdefine  
SO: Serial Output  
SO is the serial data output pin. This pin is used to transfer  
data out of the 25C11/03/05/09/17. During a read cycle,  
data is shifted out on the falling edge of the serial clock for  
Figure 1. Sychronous Data Timing  
16  
1
VCC  
HOLD  
NC  
NC  
NC  
NC  
CS  
SO  
NC  
NC  
NC  
NC  
WP  
VSS  
2
3
4
5
6
7
8
15  
14  
13  
12  
11  
10 SCK  
9 SI  
Note: Dashed Line= mode (1, 1) – – – –  
INSTRUCTION SET  
Instruction  
Opcode  
Operation  
WREN  
WRDI  
0000 0110  
0000 0100  
0000 0101  
0000 0001  
Enable Write Operations  
Disable Write Operations  
Read Status Register  
Write Status Register  
Read Data from Memory  
Write Data to Memory  
RDSR  
WRSR  
READ  
WRITE  
(1)  
0000 X011  
0000 X010  
(1)  
(2)(3)  
Power-Up Timing  
Symbol  
Parameter  
Max.  
Units  
ms  
tPUR  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
tPUW  
ms  
Note:  
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05  
(2) This parameter is tested initially and after a design or process change that affects the parameter.  
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1017, Rev. L  
4

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