Datasheet > CAT25010SE-1.8

CAT25010SE-1.8

更新时间： 2025-07-19 17:39:23

品牌	Logo	应用领域
安森美 - ONSEMI		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
18页	199K
描述
128X8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8

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数据手册

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CAT25010SE-1.8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.05
最大时钟频率 (fCLK)：	1 MHz	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.9 mm
内存密度：	1024 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	128 words
字数代码：	128	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	128X8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.75 mm	串行总线类型：	SPI
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	1.8 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
最长写入周期时间 (tWC)：	5 ms	Base Number Matches：	1

CAT25010SE-1.8 数据手册

CAT25010, CAT25020, CAT25040

Pin Description

Functional Description

The CAT25010/20/40 devices support the Serial

Peripheral Interface (SPI) bus protocol, modes (0,0) and

(1,1). The device contains an 8−bit instruction register. The

instruction set and associated op−codes are listed in Table 9.

Reading data stored in the CAT25010/20/40 is

accomplished by simply providing the READ command and

an address. Writing to the CAT25010/20/40, in addition to

a WRITE command, address and data, also requires

enabling the device for writing by first setting certain bits in

a Status Register, as will be explained later.

SI: The serial data input pin accepts op−codes, addresses

and data. In SPI modes (0,0) and (1,1) input data is latched

on the rising edge of the SCK clock input.

SO: The serial data output pin is used to transfer data out of

the device. In SPI modes (0,0) and (1,1) data is shifted out

on the falling edge of the SCK clock.

SCK: The serial clock input pin accepts the clock provided

by the host and used for synchronizing communication

between host and CAT25010/20/40.

CS: The chip select input pin is used to enable/disable the

CAT25010/20/40. When CS is high, the SO output is

tri−stated (high impedance) and the device is in Standby

Mode (unless an internal write operation is in progress).

Every communication session between host and

CAT25010/20/40 must be preceded by a high to low transition

and concluded with a low to high transition of the CS input.

After a high to low transition on the CS input pin, the

CAT25010/20/40 will accept any one of the six instruction

op−codes listed in Table 9 and will ignore all other possible

8−bit combinations. The communication protocol follows

the timing from Figure 2.

Table 9. INSTRUCTION SET (Note 13)

Instruction

WREN

WRDI

Opcode

0000 0110

0000 0100

0000 0101

0000 0001

0000 X011

0000 X010

Operation

WP: The write protect input pin will allow all write

operations to the device when held high. When WP pin is

tied low all write operations are inhibited.

Enable Write Operations

Disable Write Operations

Read Status Register

Write Status Register

Read Data from Memory

Write Data to Memory

HOLD: The HOLD input pin is used to pause transmission

between host and CAT25010/20/40, without having to

retransmit the entire sequence at a later time. To pause,

HOLD must be taken low and to resume it must be taken

back high, with the SCK input low during both transitions.

When not used for pausing, the HOLD input should be tied

RDSR

WRSR

READ

WRITE

13.X = 0 for CAT25010, CAT25020. X = A8 for CAT25040

to V , either directly or through a resistor.

CSS

CNH

CSH

CNS

SCK

VALID

DIS

HI−Z

VALID

OUT

Figure 2. Synchronous Data Timing

Status Register

The Status Register, as shown in Table 10, contains a

number of status and control bits.

Write Enable state and when set to 0, the device is in a Write

Disable state.

The RDY (Ready) bit indicates whether the device is busy

with a write operation. This bit is automatically set to 1 during

an internal write cycle, and reset to 0 when the device is ready

to accept commands. For the host, this bit is read only.

The WEL (Write Enable Latch) bit is set/reset by the

WREN/WRDI commands. When set to 1, the device is in a

The BP0 and BP1 (Block Protect) bits determine which

blocks are currently write protected. They are set by the user

with the WRSR command and are non−volatile. The user is

allowed to protect a quarter, one half or the entire memory,

by setting these bits according to Table 11. The protected

blocks then become read−only.

http://onsemi.com

1 2 3 456 7 8...18

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与CAT25010SE-1.8相关器件

型号	品牌	获取价格	描述	数据表
CAT25010SE-1.8REV-B	CATALYST	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
CAT25010SE-1.8REV-C	ONSEMI	获取价格	128X8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8
CAT25010SE-1.8REV-C	CATALYST	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
CAT25010SE-1.8TE13	ONSEMI	获取价格	128X8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8
CAT25010SE-1.8TE13REV-B	CATALYST	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
CAT25010SE-1.8TE13REV-C	ONSEMI	获取价格	IC 128 X 8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8, Programmable ROM
CAT25010SE-REV-B	CATALYST	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
CAT25010SE-REV-C	ONSEMI	获取价格	128X8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8
CAT25010SE-REV-C	CATALYST	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO8, SOIC-8
CAT25010SE-TE13	ONSEMI	获取价格	128X8 SPI BUS SERIAL EEPROM, PDSO8, SOIC-8

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