CAT24WC01/02/04/08/16
Not Recommended for New Design,
Replace with CAT24C01
the Master is allowed to send up to fifteen additional
bytes. After each byte has been transmitted the
CAT24WC01/02/04/08/16 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC01/
02/04/08/16 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
If the Master transmits more than sixteen bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programmingcyclebegins.Atthispointallreceiveddata
is written to the CAT24WC01/02/04/08/16 in a single
write cycle.
READ OPERATIONS
The READ operation for the CAT24WC01/02/04/08/16
is initiated in the same manner as the write operation
with the one exception that the R/W bit is set to a one.
ThreedifferentREADoperationsarepossible:Immediate
AddressREAD, SelectiveREADandSequentialREAD.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24WC01/02/04/08/16 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
addressforawriteoperation. IftheCAT24WC01/02/04/
08/16isstillbusywiththewriteoperation, noACKwillbe
returned. IftheCAT24WC01/02/04/08/16hascompleted
thewriteoperation, an ACKwillbereturnedandthehost
Immediate Address Read
The CAT24WC01/02/04/08/16’s address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ or
WRITEaccesswastoaddressN,theREADimmediately
following would access data from address N+1. If N=E
(where E = 255 for 24WC02, 511 for 24WC04, 1023 for
24WC08, and 2047 for 24WC16), then the counter will
'wrap around' to address 0 and continue to clock out
data. If N = E (where E = 127 for the CAT24WC01) the
counter will not 'wrap around'.
can then proceed with the next read or write operation.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
*
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16
* = Don't care for CAT24WC01
24WCXX F09
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1022, Rev. N
7