Datasheet > CAT24WC16GLE-REV-F

CAT24WC16GLE-REV-F

更新时间： 2024-02-07 22:34:52

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
14页	1126K
描述
EEPROM, 2KX8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8

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技术参数
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CAT24WC16GLE-REV-F 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.78
最大时钟频率 (fCLK)：	0.1 MHz	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e4	长度：	9.59 mm
内存密度：	16384 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	2048 words
字数代码：	2000	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	2KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	4.57 mm	串行总线类型：	I2C
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	3 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	NICKEL PALLADIUM GOLD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	7.62 mm
最长写入周期时间 (tWC)：	10 ms	Base Number Matches：	1

CAT24WC16GLE-REV-F 数据手册

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CAT24WC01/02/04/08/16

Not Recommended for New Design,

Replace with CAT24C01

using either CAT24WC01 or CAT24WC02 device. All

three address pins are used for these densities. If only

one CAT24WC01 or CAT24WC02 is addressed on the

bus, all three address pins (A0, A1and A2) can be left

stable whenever the clock line is high. Any changes

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

START Condition

floating or connected to V_SS

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDAwhenSCLisHIGH. TheCAT24WC01/02/04/08/16

monitortheSDAandSCLlinesandwillnotresponduntil

this condition is met.

A total of four devices can be addressed on a single bus

when using CAT24WC04 device. Only A1 and A2

address pins are used with this device. The A0 address

pin is a no connect pin and can be tied to V_SSor left

floating. If only one CAT24WC04 is being addressed on

thebus, theaddresspins(A1andA2)canbeleftfloating

or connected to V_SS.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

Only two devices can be cascaded when using

CAT24WC08. The only address pin used with this

device is A2. The A0 and A1 address pins are no

connectpinsandcanbetiedtoV_SSorleftfloating. Ifonly

one CAT24WC08 is being addressed on the bus, the

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are fixed

as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).

Thenextthreesignificantbits(A2,A1,A0)arethedevice

addressbitsanddefinewhichdeviceorwhichpartofthe

devicetheMasterisaccessing. UptoeightCAT24WC01/

02, four CAT24WC04, two CAT24WC08, and one

CAT24WC16 may be individually addressed by the

system. The last bit of the slave address specifies

whether a Read or Write operation is to be performed.

When this bit is set to 1, a Read operation is selected,

and when set to 0, a Write operation is selected.

addresspin(A2)canbeleftfloatingorconnected toV_SS

The CAT24WC16 is a stand alone device. In this case,

all address pins (A0, A1and A2) are no connect pins and

can be tied to V_SSor left floating.

WP: Write Protect

If the WP pin is tied to V_CCthe entire memory array

becomes Write Protected (READ only). When the WP

pin is tied to V_SSor left floating normal read/write

operations are allowed to the device.

I²C Bus Protocol

ThefollowingdefinesthefeaturesoftheI²Cbusprotocol:

After the Master sends a START condition and the slave

address byte, the CAT24WC01/02/04/08/16 monitors

the bus and responds with an acknowledge (on the SDA

line) when its address matches the transmitted slave

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

5020 FHD F06

Characteristics subject to change without notice

Doc. No. 1022, Rev. N

1 2 3 456 7 8...14

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与CAT24WC16GLE-REV-F相关器件

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CAT24WC16GLETE13F	CATALYST	1K/2K/4K/8K/16K-Bit Serial EEPROM	获取价格
CAT24WC16GLI-1.8	ONSEMI	IC,SERIAL EEPROM,2KX8,CMOS,DIP,8PIN,PLASTIC	获取价格
CAT24WC16GLI-1.8REV-D	ONSEMI	IC,SERIAL EEPROM,2KX8,CMOS,DIP,8PIN,PLASTIC	获取价格
CAT24WC16GLI-1.8REV-F	ONSEMI	IC,SERIAL EEPROM,2KX8,CMOS,DIP,8PIN,PLASTIC	获取价格
CAT24WC16GLI-REV-F	CATALYST	EEPROM, 2KX8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8	获取价格
CAT24WC16GLITE13F	CATALYST	1K/2K/4K/8K/16K-Bit Serial EEPROM	获取价格

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