CAT24WC16GLA-REV-F

更新时间： 2024-01-28 00:37:21

品牌	Logo	应用领域
CATALYST		可编程只读存储器
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9页	48K
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CAT24WC01/02/04/08/16

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The CAT24WC01/02/04/08/16 supports the I²C Bus

data transmission protocol. This Inter-Integrated Circuit

Bus protocol defines any device that sends data to the

bus to be a transmitter and any device receiving data to

be a receiver. Data transfer is controlled by the Master

device which generates the serial clock and all START

andSTOPconditionsforbusaccess.TheCAT24WC01/

02/04/08/16 operates as a Slave device. Both the Mas-

ter and Slave devices can operate as either transmitter

or receiver, but the Master device controls which mode

is activated. A maximum of 8 devices (24WC01 and

24WC02), 4 devices (24WC04), 2 devices (24WC08)

and 1 device (24WC16) may be connected to the bus as

determinedbythedeviceaddressinputsA0,A1,andA2.

SCL: Serial Clock

The CAT24WC01/02/04/08/16 serial clock input pin is

used to clock all data transfers into or out of the device.

This is an input pin.

SDA: Serial Data/Address

The CAT24WC01/02/04/08/16 bidirectional serial data/

address pin is used to transfer data into and out of the

device. The SDA pin is an open drain output and can be

wire-ORed with other open drain or open collector

outputs.

A0, A1, A2: Device Address Inputs

These inputs set device address when cascading mul-

tiple devices. When these pins are left floating the

default values are zeros (except for the 24WC01).

A maximum of eight devices can be cascaded when

Figure 1. Bus Timing

HIGH

LOW

SCL

SU:STA

HD:DAT

HD:STA

SU:DAT

SU:STO

BUF

SDA IN

SDA OUT

5020 FHD F03

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

5020 FHD F04

Figure 3. Start/Stop Timing

SDA

SCL

5020 FHD F05

START BIT

STOP BIT

Doc. No. 25051-00 3/98 S-1

1 2 345 6 7...9

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