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CAT24C161JI-42 PDF预览

CAT24C161JI-42

更新时间： 2024-02-05 11:34:28
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 73K
描述
EEPROM, 2KX8, Serial, CMOS, PDSO8

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CAT24C161JI-42 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：SOP, SOP8,.25Reach Compliance Code：unknown
风险等级：5.92Is Samacsys：N
数据保留时间-最小值：100耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010MMMRJESD-30 代码：R-PDSO-G8
JESD-609代码：e0内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
端子数量：8字数：2048 words
字数代码：2000最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
电源：5 V认证状态：Not Qualified
串行总线类型：I2C最大待机电流：0.00005 A
子类别：EEPROMs标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL写保护：HARDWARE
Base Number Matches：1

CAT24C161JI-42 数据手册

 浏览型号CAT24C161JI-42的Datasheet PDF文件第6页浏览型号CAT24C161JI-42的Datasheet PDF文件第7页浏览型号CAT24C161JI-42的Datasheet PDF文件第8页浏览型号CAT24C161JI-42的Datasheet PDF文件第10页浏览型号CAT24C161JI-42的Datasheet PDF文件第11页浏览型号CAT24C161JI-42的Datasheet PDF文件第12页 
Advanced Information  
Acknowledge Polling  
CAT24CXX1/XX2  
protected and becomes read only. The CAT24CXXX  
will accept both slave and byte addresses, but the  
memory location accessed is protected from program-  
ming by the device's failure to send an acknowledge  
after the first byte of data is received.  
Disabling of the inputs can be used to take advantage of  
the typical write cycle time. Once the stop condition is  
issued to indicate the end of the host’s write operation,  
CAT24CXXX initiates the internal write cycle. ACK poll-  
ing can be initiated immediately. This involves issuing  
the start condition followed by the slave address for a  
writeoperation. IfCAT24CXXXisstillbusywiththewrite  
operation, no ACK will be returned. If  
CAT24CXXX has completed the write operation, an  
ACK will be returned and the host can then proceed with  
the next read or write operation.  
READ OPERATIONS  
The READ operation for the CAT24CXXX is initiated in  
the same manner as the write operation with one excep-  
tion, that R/W bit is set to one. Three different READ  
operations are possible: Immediate/Current Address  
READ,Selective/Random READandSequential READ.  
WRITE PROTECTION  
The Write Protection feature allows the user to protect  
against inadvertent programming of the memory array.  
If the WP pin is tied to VCC, the entire memory array is  
Figure 9. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
24C1601Fig.8  
Doc. No. 25079-00 8/99 M-1  
9
1...6789101112

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