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CAT24C021PA-42

更新时间： 2024-02-27 22:37:34
品牌 Logo 应用领域
CATALYST 光电二极管外围集成电路
页数 文件大小 规格书
12页 71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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CAT24C021PA-42 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.92
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
长度：9.27 mm端子数量：8
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压：6 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT

CAT24C021PA-42 数据手册

 浏览型号CAT24C021PA-42的Datasheet PDF文件第6页浏览型号CAT24C021PA-42的Datasheet PDF文件第7页浏览型号CAT24C021PA-42的Datasheet PDF文件第8页浏览型号CAT24C021PA-42的Datasheet PDF文件第9页浏览型号CAT24C021PA-42的Datasheet PDF文件第11页浏览型号CAT24C021PA-42的Datasheet PDF文件第12页 
CAT24CXX1/XX2  
Immediate/Current Address Read  
and sends teh 8-bit byte requested. The master device  
does not send an acknowledge but will generate a  
STOP condition.  
The CAT24CXXX’s address counter contains the  
address of the last byte accessed, incremented by one.  
In other words, if the last READ or WRITE access was  
to address N, the READ immediately following would  
accessdatafromaddressN+1. IfN=E(whereE=255for  
the CAT24C021/022, E=511 for the CAT24C041/042,  
E=1023 for the CAT24C081/082 and E=2047 for the  
CAT24C161/162) then the counter will ‘wrap around’ to  
address 0 and continue to clock out data. After the  
CAT24CXX3 receives its slave address information  
(with the R/W bit set to one), it issues an acknowledge,  
then transmits the 8-bit byte requested. The master  
device does not send an acknowledge, but will generate  
a STOP condition.  
Sequential Read  
The Sequential READ operation can be initiated by  
eithertheImmediateAddressREADorSelectiveREAD  
operations. After the CAT24CXXX sends the inital 8-bit  
byte requested, the Master will responds with an  
acknowledge which tells the device it requires more  
data. The CAT24CXXX will continue to output an 8-bit  
byte for each acknowledge, thus sending the STOP  
condition.  
The data being transmitted from the CAT24CXXX is  
outputtedsequentiallywithdatafromaddressNfollowed  
bydatafromaddressN+1.TheREADoperationaddress  
counter increments all of the CAT24CXXX address bits  
so that the entire memory array can be read during one  
operation. If more than E (where E=255 for the  
CAT24C021/022, E=511 for the CAT24C041/042,  
E=1023 for the CAT24C081/082 and E=2047 for the  
CAT24C161/162) bytes are read out, the counter will  
‘wrap around’ and continue to clock out data bytes.  
Selective/Random Read  
Selective/Random READ operations allow the Master  
device to select at random any memory location for a  
READ operation. The Master device first performs a  
‘dummy’writeoperationbysendingtheSTARTcondition,  
slave address and byte addresses of the location it  
wishes to read. After the CAT24CXXX acknowledges,  
the Master device sends the START condition and the  
slaveaddressagain,thistimewiththeR/Wbitsettoone.  
The CAT24CXXX then responds with its acknowledge  
Figure 10. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n  
A
C
K
24C1601Fig.9  
Figure 11. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24C1601Fig.10  
Doc. No. 3000, Rev. A  
10  
1...789101112

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