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CAT1163LI-25GT3

更新时间： 2024-02-17 01:13:38
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 175K
描述
EEPROM, 2KX8, Serial, CMOS, PDIP8

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中文翻译

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CAT1163LI-25GT3 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：DIP, DIP8,.3Reach Compliance Code：unknown
风险等级：5.84数据保留时间-最小值：100
耐久性：1000000 Write/Erase CyclesI2C控制字节：1010MMMR
JESD-30 代码：R-PDIP-T8内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
端子数量：8字数：2048 words
字数代码：2000最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
电源：3/5 V认证状态：Not Qualified
串行总线类型：I2C最大待机电流：0.00004 A
子类别：EEPROMs最大压摆率：0.003 mA
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
写保护：HARDWAREBase Number Matches：1

CAT1163LI-25GT3 数据手册

 浏览型号CAT1163LI-25GT3的Datasheet PDF文件第5页浏览型号CAT1163LI-25GT3的Datasheet PDF文件第6页浏览型号CAT1163LI-25GT3的Datasheet PDF文件第7页浏览型号CAT1163LI-25GT3的Datasheet PDF文件第9页浏览型号CAT1163LI-25GT3的Datasheet PDF文件第10页浏览型号CAT1163LI-25GT3的Datasheet PDF文件第11页 
CAT1163  
Acknowledge  
receiving another acknowledge from the Slave, the  
Master device transmits the data to be written into the  
addressed memory location. The CAT1163 acknow–  
ledges once more and the Master generates the STOP  
condition. At this time, the device begins an internal  
programming cycle to non-volatile memory. While the  
cycle is in progress, the device will not respond to any  
request from the Master device.  
After a successful data transfer, each receiving  
device is required to generate an acknowledge. The  
acknowledging device pulls down the SDA line  
during the ninth clock cycle, signaling that it received  
the 8 bits of data.  
The CAT1163 responds with an acknowledge after  
receiving a START condition and its slave address.  
If the device has been selected along with a write  
operation, it responds with an acknowledge after  
receiving each 8-bit byte.  
Page Write  
The CAT1163 writes up to 16 bytes of data in a single  
write cycle, using the Page Write operation. The page  
write operation is initiated in the same manner as the  
byte write operation, however instead of terminating  
after the initial byte is transmitted, the Master is allowed  
to send up to 15 additional bytes. After each byte has  
been transmitted, the CAT1163 will respond with an  
acknowledge and internally increment the lower order  
address bits by one. The high order bits remain  
unchanged.  
When the CAT1163 begins a READ mode it  
transmits 8 bits of data, releases the SDA line and  
monitors the line for an acknowledge. Once it  
receives this acknowledge, the CAT1163 will  
continue to transmit data. If no acknowledge is sent  
by the Master, the device terminates data transmis-  
sion and waits for a STOP condition.  
If the Master transmits more than 16 bytes before  
sending the STOP condition, the address counter  
‘wraps around,’ and previously transmitted data will be  
overwritten.  
WRITE OPERATIONS  
Byte Write  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information  
¯¯  
(with the R/W bit set to zero) to the Slave device.  
When all 16 bytes are received, and the STOP  
condition has been sent by the Master, the internal  
programming cycle begins. At this point, all received  
data is written to the CAT1163 in a single write cycle.  
After the Slave generates an acknowledge, the  
Master sends a 8-bit address that is to be written  
into the address pointers of the CAT1163. After  
Figure 7. Byte Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
DATA n  
DATA n+1  
DATA n+15  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 3003 Rev. E  
8
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
1...567891011...14

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