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CAT1163LI-25 PDF预览

CAT1163LI-25

更新时间： 2024-01-10 02:31:37
品牌 Logo 应用领域
CATALYST 微控制器和处理器外围集成电路uCs集成电路uPs集成电路监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 151K
描述
Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

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CAT1163LI-25 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：DIP包装说明：DIP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.08
JESD-30 代码：R-PDIP-T8JESD-609代码：e4
长度：9.27 mm端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：5.33 mm最大供电电压：6 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.62 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

CAT1163LI-25 数据手册

 浏览型号CAT1163LI-25的Datasheet PDF文件第6页浏览型号CAT1163LI-25的Datasheet PDF文件第7页浏览型号CAT1163LI-25的Datasheet PDF文件第8页浏览型号CAT1163LI-25的Datasheet PDF文件第10页浏览型号CAT1163LI-25的Datasheet PDF文件第11页浏览型号CAT1163LI-25的Datasheet PDF文件第12页 
CAT1163  
Acknowledge Polling  
READ OPERATIONS  
Disabling of the inputs can be used to take  
advantage of the typical write cycle time. Once the  
stop condition is issued to indicate the end of the  
host’s write opration, the CAT1163 initiates the  
internal write cycle. ACK polling can be initiated  
immediately. This involves issuing the start condition  
followed by the slave address for a write operation. If  
the CAT1163 is still busy with the write operation, no  
ACK will be returned. If a write operation has  
completed, an ACK will be returned and the host can  
then proceed with the next read or write operation.  
The READ operation for the CAT1163 is initiated in the  
same manner as the write operation with one exception,  
¯¯  
that R/W bit is set to one. Three different READ ope–  
rations are possible: Immediate/Current Address READ,  
Selective/Random READ and Sequential READ.  
Immediate/Current Address Read  
The CAT1163’s address counter contains the address  
of the last byte accessed, incremented by one. In other  
words, if the last READ or WRITE access was to  
address N, the READ immediately following would  
access data from address N+1. For all devices,  
N=E=2047. The counter will wrap around to Zero and  
continue to clock out valid data for the 16K devices.  
After the CAT1163 receives its slave address  
WRITE PROTECTION  
The Write Protection feature allows the user to  
protect against inadvertent memory array program-  
ming. If the WP pin is tied to VCC, the entire memory  
array is protected and becomes read only. The  
CAT1163 will accept both slave and byte addresses,  
but the memory location accessed is protected from  
programming by the device’s failure to send an  
acknowledge after the first byte of data is received.  
¯¯  
information (with the R/W bit set to one), it issues an  
acknowledge, then transmits the 8-bit byte requested.  
The master device does not send an acknowledge, but  
will generate a STOP condition.  
Figure 9. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
9
Doc. No. 3003 Rev. E  
1...6789101112...14

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