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CAT1163LI-25 PDF预览

CAT1163LI-25

更新时间: 2024-01-06 05:07:17
品牌 Logo 应用领域
CATALYST 微控制器和处理器外围集成电路uCs集成电路uPs集成电路监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 151K
描述
Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

CAT1163LI-25 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.08
JESD-30 代码:R-PDIP-T8JESD-609代码:e4
长度:9.27 mm端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:5.33 mm最大供电电压:6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CAT1163LI-25 数据手册

 浏览型号CAT1163LI-25的Datasheet PDF文件第3页浏览型号CAT1163LI-25的Datasheet PDF文件第4页浏览型号CAT1163LI-25的Datasheet PDF文件第5页浏览型号CAT1163LI-25的Datasheet PDF文件第7页浏览型号CAT1163LI-25的Datasheet PDF文件第8页浏览型号CAT1163LI-25的Datasheet PDF文件第9页 
CAT1163  
Hardware Data Protection  
whenever VCC falls below (power down) VTH or  
until VCC reaches the reset threshold (power up)  
VTH. Any attempt to access the internal EEPROM  
is not recognized and an ACK will not be sent on  
The CAT1163 is designed with the following hardware  
data protection features to provide a high degree of  
data integrity.  
¯¯¯¯¯¯  
the SDA line when RESET or RESET is active.  
(1) The CAT1163 features a WP pin. When the WP  
pin is tied high the entire memory array becomes  
write protected (read only).  
(2) The VCC sense provides write protection when VCC  
falls below the reset threshold value (VTH). The  
VCC lock out inhibits writes to the serial EEPROM  
Reset Threshold Voltage  
The CAT1163 is offered with five reset threshold  
voltage ranges. They are 4.50 ÷ 4.75V, 4.25 ÷ 4.50V,  
3.00 ÷ 3.15V, 2.85 ÷ 3.00V and 2.55 ÷ 2.70V.  
Figure 2. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
t
DH  
AA  
SDA OUT  
Figure 3. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
Figure 4. Start/Stop Timing  
SDA  
SCL  
START BIT  
STOP BIT  
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
6
Doc. No. 3003 Rev. E  

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