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CAT1021YE-42TE13 PDF预览

CAT1021YE-42TE13

更新时间: 2024-11-15 18:18:31
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
20页 193K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, LEAD AND HALOGEN FREE, TSSOP-8

CAT1021YE-42TE13 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.07
Is Samacsys:N可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.4 mm
湿度敏感等级:1信道数量:1
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

CAT1021YE-42TE13 数据手册

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CAT1021, CAT1022,  
CAT1023  
Supervisory Circuits with  
I2C Serial 2k-bit CMOS  
EEPROM, Manual Reset and  
Watchdog Timer  
http://onsemi.com  
Description  
The CAT1021, CAT1022 and CAT1023 are complete memory and  
supervisory solutions for microcontrollerbased systems. A 2kbit  
serial EEPROM memory and a system power supervisor with  
brownout protection are integrated together in low power CMOS  
PDIP8  
CASE 646AA  
TSSOP8  
CASE 948S  
2
technology. Memory interface is via a 400 kHz I C bus.  
The CAT1021 and CAT1023 provide a precision VCC sense circuit  
and two open drain outputs: one (RESET) drives high and the other  
(RESET) drives low whenever VCC falls below the reset threshold  
voltage. The CAT1022 has only a RESET output and does not have a  
Write Protect input. The CAT1021 also has a Write Protect input  
(WP). Write operations are disabled if WP is connected to a logic high.  
All supervisors have a 1.6 second watchdog timer circuit that resets  
a system to a known state if software or a hardware glitch halts or  
“hangs” the system. For the CAT1021 and CAT1022, the watchdog  
timer monitors the SDA signal. The CAT1023 has a separate watchdog  
timer interrupt input pin, WDI.  
The power supply monitor and reset circuit protect memory and  
system controllers during power up/down and against brownout  
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V  
systems. If power supply voltages are out of tolerance reset signals  
become active, preventing the system microcontroller, ASIC or  
peripherals from operating. Reset signals become inactive typically  
200 ms after the supply voltage exceeds the reset threshold level. With  
both active high and low reset signals, interface to microcontrollers  
and other ICs is simple. In addition, the RESET pin or a separate input,  
MR, can be used as an input for pushbutton manual reset capability.  
SOIC8  
CASE 751BD  
MSOP8  
CASE 846AD  
TDFN8  
CASE 511AL  
ORDERING INFORMATION  
For Ordering Information details, see page 13.  
The onchip, 2kbit EEPROM memory features a 16byte page. In addition, hardware data protection is provided by a VCC  
sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset  
threshold during power up.  
Available packages include an 8pin PDIP and surface mount 8pin SO, 8pin TSSOP, 8pin TDFN and 8pin MSOP  
packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint options are 3 x 3 mm.  
Features  
Precision Power Supply Voltage Monitor  
Builtin Inadvertent Write Protection  
WP Pin (CAT1021)  
5 V, 3.3 V and 3 V Systems  
Five Threshold Voltage Options  
1,000,000 Program/Erase Cycles  
Manual Reset Input  
Watchdog Timer  
Active High or Low Reset  
Valid Reset Guaranteed at VCC = 1 V  
100 Year Data Retention  
Industrial and Extended Temperature Ranges  
2
400 kHz I C Bus  
8pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm  
2.7 V to 5.5 V Operation  
Footprint) Packages  
Low Power CMOS Technology  
16Byte Page Write Buffer  
TDFN Max Height is 0.8 mm  
These Devices are PbFree, Halogen Free/BFR Free  
and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
November, 2011 Rev. 18  
CAT1021/D  

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