CA3160, CA3160A
magnitude as those encountered in an operational amplifier
voltages. Figure 17 shows the voltage transfer characteristics of
the output stage for several values of load resistance.
employing a bipolar transistor input stage. The 2V differential
voltage example represents conditions when the amplifier
output state is “toggled”, e.g., as in comparator applications.
Wideband Noise
From the standpoint of low-noise performance considerations,
the use of the CA3160 is most advantageous in applications
where in the source resistance of the input signal is on the
order of 1MΩ or more. In this case, the total input-referred
noise voltage is typically only 40µV when the test circuit
amplifier of Figure 2 is operated at a total supply voltage of
15V. This value of total input-referred noise remains
Power Supply Considerations
Because the CA3160 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA3160 connected for both dual and single supply operation.
essentially constant, even though the value of source
resistance is raised by an order of magnitude. This
Dual-supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for values
of source resistance very much greater than 1MΩ, the total
noise voltage generated can be dominated by the thermal
noise contributions of both the feedback and source resistors.
equal. When the gate terminals of Q and Q are driven
increasingly positive with respect to ground, current flow
8
12
through Q (from the negative supply) to the load is
12
increased and current flow through Q (from the positive
8
supply) decreases correspondingly. When the gate terminals
of Q and Q are driven increasingly negative with respect
8
12
to ground, current flow through Q is increased and current
8
flow through Q is decreased accordingly.
12
7
V+
3
+
Single supply operation: Initially, let it be assumed that the
Q
8
value of R is very high (or disconnected), and that the input-
L
CA3160
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops
OUTPUT
STAGE
6
Q
12
across Q and Q are of equal magnitude. Figure 18 shows
typical quiescent supply-current vs supply voltage for the
CA3160 operated under these conditions.
8
12
R
L
2
-
4
NEGATIVE
SUPPLY
V-
Since the output stage is operating as a Class A amplifier, the
supply current will remain constant under dynamic operating
conditions as long as the transistors are operated in the linear
portion of their voltage-transfer characteristics (see Figure 17).
8
FIGURE 1A. DUAL POWER SUPPLY OPERATION
If either Q or Q are swung out of their linear regions toward
8
12
V+
7
cutoff (a non-linear region), there will be a corresponding
reduction in supply-current. In the extreme case, e.g., with
Terminal 8 swung down to ground potential (or tied to ground),
3
+
Q
8
NMOS transistor Q is completely cut off and the supply
12
CA3160
OUTPUT
STAGE
current to series connected transistors Q , Q goes
12
8
6
Q
12
essentially to zero. The two preceding stages in the CA3160,
however, continue to draw modest supply-current (see the
lower curve in Figure 18) even though the output stage is
strobed off. Figure 1A shows a dual-supply arrangement for the
R
L
2
-
4
output stage that can also be strobed off, assuming R = ∞, by
L
8
pulling the potential of Terminal 8 down to that of Terminal 4.
FIGURE 1B. SINGLE POWER SUPPLY OPERATION
Let it now-be assumed that a load resistance of nominal value
(e.g., 2kΩ) is connected between Terminal 6 and ground in the
circuit of Figure 1B. Let it further be assumed again that the
input-terminal bias (Terminals 2 and 3) is such that the output
FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q
8
must now supply quiescent current to both R and transistor
L
Q
, it should be apparent that under these conditions the
12
supply current must increase as an inverse function of the R
L
magnitude. Figure 20 shows the voltage-drop across PMOS
transistor Q as a function of load current at several supply
8
6
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