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C9836AY

更新时间： 2024-02-12 15:30:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
20页 321K
描述
Processor Specific Clock Generator, CMOS, PDSO48, SSOP-48

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C9836AY 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.8
Is Samacsys：NJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：15.875 mm
端子数量：48封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：2.794 mm表面贴装：YES
技术：CMOS端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

C9836AY 数据手册

 浏览型号C9836AY的Datasheet PDF文件第14页浏览型号C9836AY的Datasheet PDF文件第15页浏览型号C9836AY的Datasheet PDF文件第16页浏览型号C9836AY的Datasheet PDF文件第17页浏览型号C9836AY的Datasheet PDF文件第19页浏览型号C9836AY的Datasheet PDF文件第20页 
+/+…when timing is critical  
C9836  
Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems  
Preliminary  
Suggested Oscillator Crystal Parameters  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
MHz  
PPM  
PPM  
Conditions  
Frequency  
Fo  
14.17  
14.31818  
14.46  
Tolerance  
TC  
-
-
-
-
-
-
-
+/-100  
Note 1  
Frequency Stability  
Operating Mode  
Load Capacitance  
TS  
+/- 100  
Stability (TA -10 to +60C) Note 1  
Parallel Resonant, Note 1  
The crystal’s rated load. Note 1  
Note 2  
-
-
-
-
-
CXTAL  
RESR  
20  
40  
pF  
Effective Series  
Ohms  
Resistance (ESR)  
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen  
crystal meets or exceeds these specifications  
Note 2: Larger values may cause this device to exhibit oscillator startup problems  
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the  
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit trace  
capacitance (CPCB), and any onboard discrete load capacitance (CDISC).  
The following formula and schematic illustrates the application of the loading specification of a crystal (CXTAL)for a design.  
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC  
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC  
)
)
Where:  
CXTAL  
= the load rating of the crystal  
CXOUTFTG = the clock generators XIN pin effective device internal capacitance to ground  
CXOUTFTG = the clock generators XOUT pin effective device internal capacitance to ground  
CXINPCB  
CXOUTPCB = the effective capacitance to ground of the crystal to device PCB trace  
CXINDISC = any discrete capacitance that is placed between the XIN pin and ground  
= the effective capacitance to ground of the crystal to device PCB trace  
CXOUTDISC = any discrete capacitance that is placed between the XOUT pin and ground  
XIN  
CXINPCB  
CXINDISC  
CXINFTG  
CXOUTPCB  
CXOUTDISC  
CXOUTFTG  
XOUT  
Clock Generator  
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each  
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:  
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) = 40 x 40 = 1600  
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) 40 + 40 80  
= 20pF  
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you  
should specify a parallel cut crystal that is designed to work into a load of 20pF.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
Rev 1.0  
3/30/2000  
Page 18 of 20  
1...151617181920

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