Datasheet > C9836AY

C9836AY

更新时间： 2024-01-03 04:31:32

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
20页	321K
描述
Processor Specific Clock Generator, CMOS, PDSO48, SSOP-48

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中文翻译

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技术参数
数据手册

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C9836AY 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	15.875 mm
端子数量：	48	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	认证状态：	Not Qualified
座面最大高度：	2.794 mm	表面贴装：	YES
技术：	CMOS	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	宽度：	7.5 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

C9836AY 数据手册

+/+…when timing is critical

C9836

Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems

Preliminary

133MHz Host

100MHz Host

66MHz Host

Symbol

Parameter

Units

Min

Max

Min

69.8413

1.0

Max

71.0

4.0

Min

69.8413

1.0

Max

71.0

4.0

TPeriod

Tr / Tf

REF period^5,6

REF rise and fall times⁷

REF Cycle to Cycle Jitter⁶

69.8413

71.0

4.0

1.0

TCCJ

1000

10.0

1000

10.0

1000

10.0

tpZL, tpZH

tpLZ, tpHZ

tstable

Output enable delay (all outputs)⁸

Output disable delay (all outputs)¹³

All clock Stabilization from power-up¹²

Duty Cycle for All outputs¹⁴

1.0

Tduty

Note 5: This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818MHz

Note 6: All outputs loaded as per Table 6 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at

1.25V for 2.5V signals (figures 8a and 8b).

Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V

and 2.0V for 2.5V signals (see Figures 8a and 8b)

Note 8: Measured from when both SEL1 and SEL0 are switched to high (enable).

Note 9: This measurement is applicable with Spread ON or Spread OFF.

Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see

Figures 8a and 8b)

Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.

Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency

output is stable and operating within the specifications

Note 13:Measured from when both SEL1 and SEL0 are switched to low (disable).

Note 14: Device designed for Typical Duty Cycle of 50%.

Clock Name

Max Load (in

pF)

CPU(0,1), REF(0:2)

PCI(_F, 1:7), SDRAM(0:3), DCLK, 3V66(0:2)

48M_DOT

Table 6.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.0

3/30/2000

Page 15 of 20

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