Datasheet > C9817AYB

C9817AYB

更新时间： 2024-02-27 21:01:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
19页	207K
描述
Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56

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中文翻译

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技术参数
数据手册

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C9817AYB 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	56
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	R-PDSO-G56	JESD-609代码：	e0
长度：	18.415 mm	端子数量：	56
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	2.794 mm
表面贴装：	YES	技术：	CMOS
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

C9817AYB 数据手册

+/+…when timing is critical

C9817

133 MHz I²C Clock Generator for mobile Pentium^®III / Rambus Systems

Preliminary

Package Drawing and Dimensions (Cont.) 56 Pin TSSOP

NOTES:

1. Die thickness allowable is 0.279 +/- 0.0127 (0.0110

+/- .005 inches)

2. Dimensions & tolerance per ASME. Y14, 5M-1994.

3. Datum Plane H located at mold parting line and

concident with lead. Where lead exits plastic body

at bottom of parting line.

4. Datums A-B and D to be determined where

centerline between leads exits plastic body at

Datum Plane H.

5. “D” and “E” are reference datums and do not

include mode flash or protrusions, and are

measured at the bottom parting line. Mold flash or

protrusions shall not exceed 0.15mm on D and

0.25mm on E per side.

6. Dimension is the length of terminal for soldering to

a substrate.

7. Terminal positions are shown for reference only.

8. Formed leads shall be planar with respect to one

another within 0.076mm at seating plane.

9. The lead width dimension does not include Dambar

protrusion. Allowable Dambar protrusion shall be

0.08mm total in excess of the lead width dimension

located on the lower radius or the foot. Minimum

space between protrusions and an adjacent lead to

be 0.08mm for 0.50mm pitch.

10. Section “C-C” to be determined at 0.10 to 0.25mm

from the lead tip.

11. This part is compliant with JEDEC specification

MO-153, variations DB, DC, DE ED, EE, and FE.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571

WWW.IMICORP.COM

Rev 1.0

11/1/1999

Page 18 of 19

1...15 16 171819

中文翻译

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与C9817AYB相关器件

型号	品牌	获取价格	描述	数据表
C9819ATB	CYPRESS	获取价格	Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48
C9819AYB	CYPRESS	获取价格	Processor Specific Clock Generator, CMOS, PDSO48, SSOP-48
C981U103MYVDAA7317	KEMET	获取价格	Safety Standard Recognized, 900 Series, Radial Disc, Encapsulated, X1 400 VAC / Y1 250 VAC
C981U103MYVDBA7317	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro
C981U103MZVDAA7317	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro
C981U103MZVDAAWL20	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro
C981U103MZVDAAWL45	KEMET	获取价格	Ceramic Capacitor, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Through Hole Mou
C981U103MZVDBA7317	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro
C981U103MZVDBAWL35	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro
C981U103MZVDBAWL40	KEMET	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro

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