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C9817AYB

更新时间： 2024-02-02 15:14:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
19页 207K
描述
Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56

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C9817AYB 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm端子数量：56
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：2.794 mm
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

C9817AYB 数据手册

 浏览型号C9817AYB的Datasheet PDF文件第13页浏览型号C9817AYB的Datasheet PDF文件第14页浏览型号C9817AYB的Datasheet PDF文件第15页浏览型号C9817AYB的Datasheet PDF文件第17页浏览型号C9817AYB的Datasheet PDF文件第18页浏览型号C9817AYB的Datasheet PDF文件第19页 
+/+…when timing is critical  
C9817  
133 MHz I2C Clock Generator for mobile Pentium®III / Rambus Systems  
Preliminary  
Suggested Crystal Oscillator Parameters  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
MHz  
PPM  
PPM  
PPM  
Conditions  
Frequency  
Fo  
12.00  
14.31818  
16.00  
Tolerance  
TC  
-
-
-
-
-
-
-
-
+/-100  
note 1  
TS  
+/- 100  
Stability (Ta -10 to +60C) note 1  
Aging (first year @ 25C) note 1  
Parallel Resonant, note 1  
the crystals rated load. note 1  
Note 1  
TA  
-
5
-
Mode  
OM  
CL  
-
Load Capacitance  
18  
40  
-
pF  
Effective Series  
resistance (ESR)  
R1  
-
Ohms  
Power Dissipation  
Shunt Capacitance  
DL  
-
-
-
0.10  
8
mW  
pF  
note 1  
crystals internal package  
capacitance (total)  
CO  
--  
Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that  
the chosen crystal meets these specifications  
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the  
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit  
traces, the clock generator and any onboard discrete load capacitors.  
Budgeting Calculations  
Device pin capacitance: Cxtal = 36pF  
In order to meet the specification for CL = 18pF following the formula:  
Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the  
CXIN xCXOUT  
CL =  
CXIN + CXOUT  
trace between Xout and the crystal)  
In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal  
and Xout will be 36pF. Hence using the above formula:  
36pFx36pF  
CL =  
= 18pF  
36pF + 36pF  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571  
WWW.IMICORP.COM  
Rev 1.0  
11/1/1999  
Page 16 of 19  
1...13141516171819

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