C8051F042
25 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
10-Bit ADC
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Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
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±1 LSB INL; guaranteed monotonic
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Up to 25 MIPS throughput with 25 MHz system clock
Programmable throughput up to 100 ksps
13 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Expanded interrupt handler
Memory
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4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
High-Voltage Differential Amplifier
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External parallel data memory interface
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60 V common mode input range
Offset adjust from –60 to +60 V
16 gain settings from 0.05 to 16
CAN Bus 2.0B
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32 message objects
”Mailbox" implementation only interrupts CPU when needed
8-Bit ADC
Digital Peripherals
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Programmable throughput up to 500 ksps
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64 port I/O; all are 5 V tolerant
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 4, 2, 1, 0.5
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Two 12-Bit DACs
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Programmable 16-bit counter array with 6 capture/compare modules
Three Comparators
Internal Voltage Reference
Precision V Monitor/Brown-out Detector
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
DD
On-Chip JTAG Debug & Boundary Scan
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Clock Sources
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor, pro-
gram trace memory
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Internal programmable 2% oscillator: up to 25 MHz
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External oscillator: Crystal, RC, C, or Clock
Package
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Inspect/modify memory and registers
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100-pin TQFP (standard lead and lead-free packages
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
Ordering Part Numbers
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Lead-free package: C8051F042-GQ
Supply Voltage: 2.7 to 3.6 V
Standard package: C8051F042
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Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown mode
Temperature Range: –40 to +85 °C
VDD
VDD
Digital Power
UART0
P0.0
P0.7
P0
Drv
VDD
DGND
DGND
DGND
AV+
UART1
8
0
5
1
C
R
O
S
S
B
A
R
SMBus
SPI Bus
PCA
SFR Bus
P1.0/AIN1.0
P1.7/AIN1.7
Analog Power
AV+
P1
Drv
AV+
AGND
AGND
AGND
Timers
0,1,2,3,4
P2.0/CPx
P2.7/CPx
TCK
TMS
TDI
P2
Drv
Boundary Scan
JTAG
Logic
Debug HW
Port
0,1,2,3
&4
TDO
64 kB
FLASH
Reset
RST
P3.0/AIN0.6
P3.7/AIN0.7
P3
Drv
Latches
VDD
Monitor
WDT
MONEN
C
o
r
32x136
CANRAM
CTX0
CRX0
CAN
2.0B
External
Oscillator
Circuit
XTAL1
XTAL2
System
Clock
256 byte
RAM
A
ADC
M
U
X
Prog
Gain
8:1
500 ksps
(8-Bit)
VREF
VREF
VREFD
4 kB
XRAM
VREF2
e
DAC1
(12-Bit)
P2.0
DAC1
Internal
2%
Oscillator
+
-
CP0
CP1
P2.1
P2.2
P2.3
+
-
DAC0
(12-Bit)
DAC0
P2.4
P2.5
+
-
CP2
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
P4.0
A
M
U
X
ADC
100 ksps
(10-Bit)
P4
DRV
P4.4
Port 4 <from crossbar>
Bus Control
Prog
Gain
P4.5/ALE
P4.6/RD
P4.7/WR
External Data Memory Bus
Ctrl Latch
P5.0/A0
P5 Latch
Addr [7:0]
P6 Latch
P5
DRV
Address [15:0]
TEMP
SENSOR
P5.7/A7
P6.0/A8
A
P6
DRV
M
U
X
8:2
Addr [15:8]
P7 Latch
P6.7/A15
P7.0/D0
P7
DRV
HVAIN+
HVAIN-
Data [7:0]
P7.7/D7
Data Latch
HVAMP
HVREF
HVCAP
CAN 2.0B
Copyright © 2005 by Silicon Laboratories
5.5.2005