C8051F023
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
10-Bit ADC
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
-
-
-
-
-
±1 LSB INL; no missing codes
-
Up to 25 MIPS throughput with 25 MHz system clock
22 vectored interrupt sources
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
-
Memory
-
-
4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
8-Bit ADC
are reserved)
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External parallel data memory interface
-
-
-
-
±1 LSB INL; no missing codes
Programmable throughput up to 500 ksps
8 external inputs
Programmable amplifier gain: 4, 2, 1, 0.5
Digital Peripherals
-
-
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
Two 12-Bit DACs
ports available concurrently
-
Can synchronize outputs to timers for jitter-free waveform generation
-
-
-
-
Programmable 16-bit counter/timer array with 5 capture/compare mod-
ules
Two Comparators
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using Timer 3 or PCA
Internal Voltage Reference
V
Monitor/Brown-out Detector
DD
On-Chip JTAG Debug & Boundary Scan
Clock Sources
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
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-
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Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
Supply Voltage: 2.7 to 3.6 V
pods, and sockets
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Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown modes
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IEEE1149.1 compliant boundary scan
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64-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
Port I/O
Config.
VDD
DGND
DGND
DGND
Digital Power
Analog Power
P0.0
P0.7
UART0
P0
UART1
8
0
5
1
Drv
AV+
C
SMBus
AGND
P1.0/AIN1.0
P1.7/AIN1.7
R
P1
SPI Bus
PCA
Drv
O
S
S
B
A
R
TCK
TMS
TDI
Boundary Scan
Debug HW
JTAG
Logic
Timers 0,
1, 2, 4
P2.0
P2.7
TDO
P2
SFR Bus
Drv
Reset
RST
Timer 3/
RTC
VDD
64 kB
P3.0
P3.7
WDT
MONEN
P3
Monitor
P0, P1,
P2, P3
Latches
C
o
r
FLASH
Drv
External
Oscillator
Circuit
XTAL1
XTAL2
256 Byte
RAM
Crossbar
Config.
REFADC
VDD
System
Clock
Internal
4 kB
Oscillator
A
M
U
X
ADC
e
RAM
8:1
Prog
Gain
500 ksps
(8-Bit)
VREF
DAC1
VREF
External Data Memory Bus
DAC1
(12-Bit)
C
T
L
P4 Latch
Bus Control
P4
DRV
DAC0
DAC0
(12-Bit)
(REFADC)
VREFA
P5 Latch
P6 Latch
P5
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
A
d
d
r
DRV
Address Bus
Data Bus
ADC
A
M
U
X
P6
Prog
Gain
100 ksps
(10-Bit)
DRV
D
a
t
P7 Latch
TEMP
SENSOR
P7
DRV
CP0+
CP0-
CP1+
CP1-
CP0
a
CP1
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
6.15.2004
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