Datasheet > C5750X7R1H106K

C5750X7R1H106K

更新时间： 2024-11-24 12:50:47

品牌	Logo	应用领域
英特矽尔 - INTERSIL		电容器
页数	文件大小	规格书
10页	531K
描述
ISL6844 Reference Design: ISL6844EVAL3Z

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C5750X7R1H106K 数据手册

Application Note 1612

ISL6844 Reference Design: ISL6844EVAL3Z

Where:

Introduction

This document focuses on Intersil’s solution for the flyback

converter. An inexpensive approach with discrete circuitry has

been adopted instead of an integrated solution. Low cost and

optimal performance are the prime objectives.

η = Converter’s efficiency, assuming 75%

= Total output power

OUT

= Switching frequency

As a result, the peak magnitizing current = 1.06A

The transformer’s turn ratio can be determined from:

Intersil’s superior industry-standard ISL684x family of PWM

controllers would best serve the needs of this design. Some

key features of this family of parts include:

+ V ) ⋅ (1 – d )

F 2

out

-------------------------------------------------------

n =

• 40ns peak current sensing

• 1A MOSFET driver

⋅ d

MAX

(EQ. 2)

IN, MIN

+ d < 1

MAX

ISL6844 was selected for its large UVLO hysteresis, UVLO start

threshold, and the fact that the converter has been designed

for a maximum operational duty cycle of 50%, thus protecting

the IC by limiting the duty cycle in case of extreme fault

conditions.

Where:

n = Turns ratio between the primary and the secondary

windings

V = Forward drop across the diode, assuming 0.6V

Specifications

• Operating Input Voltage: 24V DC ±10%

• Output Voltage: ±15V

d = Duty cycle of diode conduction time

d T is the magnitizing current reset time. Setting d to 0.5,

2 sw

Equation 2 yields the transformer’s turn ratio of 1.

• Output Current: 100mA

+15V

VIN

• Ripple: 50mV

P-P

CIN

C_OUT1

• Switching Frequency: 300kHz

• Topology: DCM Flyback

C_OUT2

OUT

-15V

Design Procedure

RSENSE

VIN

Figure 1 shows a simplified circuit of the solution. It is

assumed that loads are balanced for both positive and

negative outputs. The turn ratio of the auxiliary winding is

chosen to be the same as the secondary winding. Figure 2

shows typical operational waveforms of a flyback converter in

discontinuous conduction mode.

ISL6844

VREG

VDD

C_AUX

GND

Determine the Maximum Duty Cycle and

Transformer Turn Ratio

FIGURE 1. SIMPLIFIED CIRCUIT

ISL6844 clamps the duty cycle to 50%. However, in this

converter design, it is assumed that the operating maximum

duty cycle, d

21.6V.

, will be 35% at the minimum input voltage of

max

Given the power level, the flyblack converter is designed to

operate in discontinuous conduction mode. The magnitizing

inductance can be calculated using Equation 1:

max

⋅ F

⋅ d

IN, MIN

-----------------------------------------

= η ⋅

2 ⋅ P

(EQ. 1)

out

21.6 ⋅ 0.35

-------------------------------------

2 ⋅ 3 ⋅ 300×10

= 0.75 ⋅

= 23.8μH

November 28, 2011

AN1612.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7...10

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与C5750X7R1H106K相关器件

型号	品牌	获取价格	描述	数据表
C5750X7R1H106K230KB	TDK	获取价格	CAP CER 10UF 50V X7R 2220
C5750X7R1H106KT	TDK	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, 15% TC, 10uF, Surfac
C5750X7R1H106M	TDK	获取价格	C Series General Application
C5750X7R1H106M(230KB)	TDK	获取价格	CAPACITOR, CERAMIC, MULTILAYER, 50 V, X7R, 10 uF, SURFACE MOUNT, 2220, CHIP, ROHS COMPLIAN
C5750X7R1H106M230KB	TDK	获取价格	Ceramic Capacitor, Multilayer, Ceramic, 50V, 20% +Tol, 20% -Tol, X7R, 15% TC, 10uF, Surfac
C5750X7R1H106MT	TDK	获取价格	暂无描述
C5750X7R1H107B020AA	TDK	获取价格	MULTILAYER CERAMIC CHIP CAPACITORS
C5750X7R1H107B030AA	TDK	获取价格	MULTILAYER CERAMIC CHIP CAPACITORS
C5750X7R1H107C020AA	TDK	获取价格	MULTILAYER CERAMIC CHIP CAPACITORS
C5750X7R1H107C030AA	TDK	获取价格	MULTILAYER CERAMIC CHIP CAPACITORS

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