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C3P-L67202V-65 PDF预览

C3P-L67202V-65

更新时间： 2024-12-01 15:32:23
品牌 Logo 应用领域
TEMIC 先进先出芯片光电二极管
页数 文件大小 规格书
16页 146K
描述
FIFO, 1KX9, 65ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

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C3P-L67202V-65 技术参数

生命周期：Transferred包装说明：0.300 INCH, PLASTIC, DIP-28
Reach Compliance Code：unknown风险等级：5.78
最长访问时间：65 ns周期时间：80 ns
JESD-30 代码：R-PDIP-T28内存密度：9216 bit
内存宽度：9功能数量：1
端子数量：28字数：1024 words
字数代码：1000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1KX9可输出：NO
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子位置：DUALBase Number Matches：1

C3P-L67202V-65 数据手册

 浏览型号C3P-L67202V-65的Datasheet PDF文件第2页浏览型号C3P-L67202V-65的Datasheet PDF文件第3页浏览型号C3P-L67202V-65的Datasheet PDF文件第4页浏览型号C3P-L67202V-65的Datasheet PDF文件第5页浏览型号C3P-L67202V-65的Datasheet PDF文件第6页浏览型号C3P-L67202V-65的Datasheet PDF文件第7页 
MATRA MHS  
L 67201/L 67202  
512 × 9 & 1K × 9 / 3.3 Volts CMOS Parallel FIFO  
Introduction  
The L67201/202 implement a first-in first-out algorithm, Using an array of eight transistors (8 T) memory cell and  
featuring asynchronous read/write operations. The FULL fabricated with the state of the art 1.0 µm lithography  
and EMPTY flags prevent data overflow and underflow. named SCMOS, the L 67201/202 combine an extremely  
The Expansion logic allows unlimited expansion in word low standby supply current (typ = 1.0 µA) with a fast  
size and depth with no timing penalties. Twin address access time at 55 ns over the full temperature range. All  
pointers automatically generate internal read and write versions offer battery backup data retention capability  
addresses, and no external address information are with a typical power consumption at less than 5 µW.  
required for the MHS FIFOs. Address pointers are  
For military/space applications that demand superior  
automatically incremented with the write pin and read  
levels of performance and reliability the L 67201/202 is  
pin. The 9 bits wide data are used in data communications  
processed according to the methods of the latest revision  
applications where a parity bit for error checking is  
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.  
necessary. The Retransmit pin reset the Read pointer to  
zero without affecting the write pointer. This is very  
useful for retransmitting data when an error is detected in  
the system.  
Features  
D First-in first-out dual port memory  
D Single supply 3.3 ± 0.3 volts  
D 512 × 9 organisation (L 67201)  
D 1024 × 9 organisation (L 67202)  
D Fast access time  
D Fully expandable by word width or depth  
D Asynchronous read/write operations  
D Empty, full and half flags in single device mode  
D Retransmit capability  
D Bi-directional applications  
55, 60, 65 ns, commercial, industrial military and  
automotive  
D Battery back-up operation 2 V data retention  
D TTL compatible  
D Wide temperature range :  
D High performance SCMOS technology  
– 55 °C to + 125 °C  
D 67201L/202L low power  
67201V/202V very low power  
Rev. C (10/11/95)  
1
1234567...16

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