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C1210C475K4R1L7186 PDF预览

C1210C475K4R1L7186

更新时间: 2024-11-24 14:54:31
品牌 Logo 应用领域
基美 - KEMET /
页数 文件大小 规格书
18页 2635K
描述
KPS SMD Comm X7R SnPb, Ceramic, 4.7 uF, 10%, 16 VDC, X7R, 1210-1

C1210C475K4R1L7186 数据手册

 浏览型号C1210C475K4R1L7186的Datasheet PDF文件第2页浏览型号C1210C475K4R1L7186的Datasheet PDF文件第3页浏览型号C1210C475K4R1L7186的Datasheet PDF文件第4页浏览型号C1210C475K4R1L7186的Datasheet PDF文件第5页浏览型号C1210C475K4R1L7186的Datasheet PDF文件第6页浏览型号C1210C475K4R1L7186的Datasheet PDF文件第7页 
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)  
KPS "L", SnPb Termination, X7R Dielectric,  
10 – 250 VDC (Commercial Grade)  
Overview  
KEMET Power Solutions (KPS) Commercial "L" with Tin/  
Lead Termination stacked capacitors utilize a proprietary  
lead-frame technology to vertically stack one or two  
multilayer ceramic chip capacitors into a single compact  
surface mount package. The attached lead-frame  
mechanically isolates the capacitor's from the printed  
circuit board, therefore offering advanced mechanical  
and thermal stress performance. Isolation also addresses  
concerns for audible, microphonic noise that may occur  
when a bias voltage is applied. A two chip stack offers  
up to double the capacitance in the same or smaller  
design footprint when compared to traditional surface  
mount MLCC devices. Providing up to 10 mm of board  
flex capability, KEMET’s tin/lead electroplating process is  
designed to meet a 5% minimum lead content and address  
concerns for a more robust and reliable lead containing  
termination system. As the bulk of the electronics industry  
moves towards RoHS compliance, KEMET continues to  
provide tin/lead terminated products for military, aerospace  
and industrial applications and will ensure customers have a  
stable and long-term source of supply. These devices provide  
lower ESR, ESL and higher ripple current capability when  
compared to other dielectric solutions.  
Combined with the stability of an X7R dielectric, KEMET’s  
KPS devices exhibit a predictable change in capacitance  
with respect to time and voltage and boast a minimal change  
in capacitance with reference to ambient temperature.  
Capacitance change is limited to ±15% from −55°C to  
+125°C.  
Benefits  
• Operating temperature range of −55°C to +125°C  
• Reliable and robust termination system  
• EIA 1210 and 2220 case sizes  
• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 63 V, 100 V and 250 V  
• Capacitance offerings ranging from 0.1 up to 47 μF  
Ordering Information  
C
2220  
C
106  
M
5
R
2
L
7186  
Rated  
Voltage Dielectric  
(VDC)  
Packaging/  
Grade  
(C-Spec)  
Case Size Specification/ Capacitance Capacitance  
Failure Rate/  
Design  
Leadframe  
Finish2  
Ceramic  
(L" x W")  
Series  
Code (pF)  
Tolerance1  
1210  
2220  
C = Standard  
Two  
K = ±10%  
M = ±20%  
8 = 10  
4 = 16  
3 = 25  
5 = 50  
M = 63  
1 = 100  
A = 250  
R = X7R 1 = KPS Single Chip Stack  
L = SnPb  
See  
"Packaging  
C-Spec  
Ordering  
Options Table"  
Significant  
Digits and  
Number of  
Zeroes  
2 = KPS Double Chip Stack (5% Pb min.)  
1 Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance.  
Single chip stacks ("1" in the 13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances.  
2 Additional leadframe finish options may be available. Contact KEMET for details.  
Built Into Tomorrow  
© KEMET Electronics Corporation • One East Broward Boulevard  
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com  
C1089_X7R_KPS_SnPb • 8/21/2023  
1

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