5秒后页面跳转
捷配首页

Datasheet > BUS-61564-35Y
BUS-61564-35Y PDF预览

BUS-61564-35Y

更新时间： 2024-11-30 23:37:39
品牌 Logo 应用领域
其他 - ETC 控制器
页数 文件大小 规格书
4页 52K
描述
Controller Miscellaneous - Datasheet Reference

阅读下载

中文翻译

获取价格

BUS-61564-35Y 数据手册

 浏览型号BUS-61564-35Y的Datasheet PDF文件第2页浏览型号BUS-61564-35Y的Datasheet PDF文件第3页浏览型号BUS-61564-35Y的Datasheet PDF文件第4页 
BUS -6 1 5 5 3  
MIL-S TD-1 5 5 3 ADVANCED INTEGRATED  
(
)
MUX AIM HYBRID  
DESCRIPTION  
FEATURES  
• Fully Intergrated Terminal  
Including:  
–Dual Transceiver  
–BC/RT/MT Protocol  
–Memory Management Unit  
–Processor lnterface Logic  
–8K x 16 RAM  
DDC’s  
Integrated Mux (AIM) Hybrid is a maximum design flexibility, memory  
complete MIL-STD-1553 Bus control lines are provided for attach-  
Controller (BC), Remote Terminal ing external RAM to the BUS-61553  
Unit (RTU), and Bus Monitor (MT) address and data buses and for dis-  
device. Packaged in a single 78-pin abling internal memory; the total  
DIP package, the BUS-61553 con- combined memory space can be  
tains dual low-power transceivers, expanded to 64K x 16. All 1553 trans-  
complete BC/RT/MT protocol logic, a fers are entirely memory-mapped;  
MIL-STD-1553-to-host interface unit thus the CPU interface requires  
BUS-61553  
Advanced shared 8K x 16 RAM. To ensure  
• CMOS and Bipolar Technologies  
and 8K x 16 RAM.  
minimal hardware and/or software  
support.  
• Internal Interrupt Status and Time  
Tag Registers  
Using an industry standard dual  
transceiver and standard status and The BUS-61553 operates over the  
control signals, the BUS-61553 sim- full military -55°C to +125°C temper-  
plifies system integration at both the ature range. Available screened to  
MIL-STD-1553 and host processor MIL-PRF-38534, the BUS-61553 is  
• High Reliability  
• 883B Processing Available  
interface levels.  
ideal for demanding military and  
industrial microprocessor-to-1553  
interface applications.  
All 1553 operations are controlled  
through the CPU access to the  
BUS-25679  
TRANSCEIVER A  
8
1
TX INH  
CLOCK IN  
DATA  
2
BUS A  
3
4
MSTRCLR  
SELECT  
STRBD  
TX  
CHANNEL A  
ENCODER/  
DECODER  
MEMORY  
TIMING  
TRANSFORMER A  
RX  
READYD  
CPU  
RD/WR  
TIMING  
RX  
MEM/REG  
EXTEN  
EXTLD  
CONTENTION  
RESOLVER  
PROTOCOL  
CONTROLLER  
INTERRUPT  
GENERATOR  
INT  
768 µs  
TIME OUT  
A15-A00  
BUS-25679  
D15-D00  
1
2
8
TX INH  
TX  
DATA  
BUS B  
4
3
CHANNEL B  
ENCODER/  
DECODER  
8K x 16  
SHARED RAM  
RTAD0  
RTAD1  
TRANSFORMER B  
RX  
PARITY  
CHECKER  
RTAD2  
RTAD3  
RTAD4  
RTAD P  
RT ADDR  
RAM  
RX  
TRANSCEIVER B  
RTPARERR  
FIGURE 1. BU-61553 BLOCK DIAGRAM  
© 1987, 1999 Data Device Corporation  
1234

中文翻译

下载PDF

与BUS-61564-35Y相关器件

型号 品牌 获取价格 描述 数据表
BUS-61564-35Z ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36 ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36K ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36L ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36Q ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36S ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36W ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36Y ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-36Z ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference
BUS-61564-37 ETC

获取价格

 		Controller Miscellaneous - Datasheet Reference

与BUS-61564-35Y相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证