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BUS-61564-28Y PDF预览

BUS-61564-28Y

更新时间： 2024-11-29 23:37:39
品牌 Logo 应用领域
其他 - ETC 控制器
页数 文件大小 规格书
4页 52K
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Controller Miscellaneous - Datasheet Reference

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BUS-61564-28Y 数据手册

 浏览型号BUS-61564-28Y的Datasheet PDF文件第2页浏览型号BUS-61564-28Y的Datasheet PDF文件第3页浏览型号BUS-61564-28Y的Datasheet PDF文件第4页 
BUS -6 1 5 5 3  
MIL-S TD-1 5 5 3 ADVANCED INTEGRATED  
(
)
MUX AIM HYBRID  
DESCRIPTION  
FEATURES  
• Fully Intergrated Terminal  
Including:  
–Dual Transceiver  
–BC/RT/MT Protocol  
–Memory Management Unit  
–Processor lnterface Logic  
–8K x 16 RAM  
DDC’s  
Integrated Mux (AIM) Hybrid is a maximum design flexibility, memory  
complete MIL-STD-1553 Bus control lines are provided for attach-  
Controller (BC), Remote Terminal ing external RAM to the BUS-61553  
Unit (RTU), and Bus Monitor (MT) address and data buses and for dis-  
device. Packaged in a single 78-pin abling internal memory; the total  
DIP package, the BUS-61553 con- combined memory space can be  
tains dual low-power transceivers, expanded to 64K x 16. All 1553 trans-  
complete BC/RT/MT protocol logic, a fers are entirely memory-mapped;  
MIL-STD-1553-to-host interface unit thus the CPU interface requires  
BUS-61553  
Advanced shared 8K x 16 RAM. To ensure  
• CMOS and Bipolar Technologies  
and 8K x 16 RAM.  
minimal hardware and/or software  
support.  
• Internal Interrupt Status and Time  
Tag Registers  
Using an industry standard dual  
transceiver and standard status and The BUS-61553 operates over the  
control signals, the BUS-61553 sim- full military -55°C to +125°C temper-  
plifies system integration at both the ature range. Available screened to  
MIL-STD-1553 and host processor MIL-PRF-38534, the BUS-61553 is  
• High Reliability  
• 883B Processing Available  
interface levels.  
ideal for demanding military and  
industrial microprocessor-to-1553  
interface applications.  
All 1553 operations are controlled  
through the CPU access to the  
BUS-25679  
TRANSCEIVER A  
8
1
TX INH  
CLOCK IN  
DATA  
2
BUS A  
3
4
MSTRCLR  
SELECT  
STRBD  
TX  
CHANNEL A  
ENCODER/  
DECODER  
MEMORY  
TIMING  
TRANSFORMER A  
RX  
READYD  
CPU  
RD/WR  
TIMING  
RX  
MEM/REG  
EXTEN  
EXTLD  
CONTENTION  
RESOLVER  
PROTOCOL  
CONTROLLER  
INTERRUPT  
GENERATOR  
INT  
768 µs  
TIME OUT  
A15-A00  
BUS-25679  
D15-D00  
1
2
8
TX INH  
TX  
DATA  
BUS B  
4
3
CHANNEL B  
ENCODER/  
DECODER  
8K x 16  
SHARED RAM  
RTAD0  
RTAD1  
TRANSFORMER B  
RX  
PARITY  
CHECKER  
RTAD2  
RTAD3  
RTAD4  
RTAD P  
RT ADDR  
RAM  
RX  
TRANSCEIVER B  
RTPARERR  
FIGURE 1. BU-61553 BLOCK DIAGRAM  
© 1987, 1999 Data Device Corporation  
1234

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