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BUF601AU/2K5 PDF预览

BUF601AU/2K5

更新时间： 2024-02-14 22:00:25
品牌 Logo 应用领域
德州仪器 - TI 放大器光电二极管
页数 文件大小 规格书
16页 198K
描述
High-Speed Buffer Amplifier 8-SOIC

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中文翻译

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BUF601AU/2K5 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：5.78
商用集成电路类型：VIDEO AMPLIFIERJESD-30 代码：R-PDSO-G8
长度：4.9 mm功能数量：1
端子数量：8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.75 mm
表面贴装：YES技术：BIPOLAR
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

BUF601AU/2K5 数据手册

 浏览型号BUF601AU/2K5的Datasheet PDF文件第7页浏览型号BUF601AU/2K5的Datasheet PDF文件第8页浏览型号BUF601AU/2K5的Datasheet PDF文件第9页浏览型号BUF601AU/2K5的Datasheet PDF文件第11页浏览型号BUF601AU/2K5的Datasheet PDF文件第12页浏览型号BUF601AU/2K5的Datasheet PDF文件第13页 
The buffer outputs are not current-limited or protected. If the  
output is shorted to ground, high currents could arise when  
the input voltage is ±3.6V. Momentary shorts to ground (a  
few seconds) should be avoided but are unlikely to cause  
permanent damage.  
+5V Pos  
C4  
2.2µF  
C2  
470nF  
BUF600AP  
1
RIN  
ROUT  
51Ω  
Out  
In  
CIRCUIT LAYOUT  
8
4
+1  
The high-frequency performance of the BUF600 and BUF601  
can be greatly affected by the physical layout of the printed  
circuit board. The following tips are offered as suggestions,  
not as absolute musts. Oscillations, ringing, poor bandwidth  
and settling, and peaking are all typical problems that plague  
high-speed components when they are used incorrectly.  
160Ω  
5
GND  
C3  
2.2µF  
C1  
470nF  
–5V Neg  
•
Bypass power supplies very close to the device pins. Use  
tantalum chip capacitors (approximately 2.2µF); a paral-  
lel 470nF ceramic chip capacitor may be added if desired.  
Surface-mount types are recommended due to their low  
lead inductance.  
FIGURE 2. Test Circuit.  
IMPEDANCE MATCHING  
The BUF600 and BUF601 provide power gain and isolation  
between source and load when used as an active tap or  
impedance matching device as illustrated in Figure 3. In this  
example, there is no output matching path between the  
buffer and the 75Ω line. Such matching is not needed when  
the distant end of the cable is properly terminated, since  
there is no reflected signal when the buffer isolates the  
source. This technique allows the full output voltage of the  
buffer to be applied to the load.  
•
•
•
PC board traces for power lines should be wide to reduce  
impedance or inductance.  
Make short and low inductance traces. The entire physi-  
cal circuit should be as small as possible.  
Use a low-impedance ground plane on the component  
side to ensure that low-impedance ground is available  
throughout the layout.  
•
•
•
Do not extend the ground plane under high-impedance  
nodes sensitive to stray capacitances, such as the buffer’s  
input terminals.  
+5V  
Sockets are not recommended, because they add signifi-  
cant inductance and parasitic capacitance. If sockets must  
be used, consider using zero-profile solderless sockets.  
2.2µF  
470nF  
Use low-inductance and surface-mounted components.  
Using all surface-mount components will offer the best  
AC performance.  
1
75Ω  
VI  
VO  
8
4
BUF  
160Ω  
300Ω  
5
•
•
A resistor (100Ω to 250Ω) in series with the input of the  
buffers may help to reduce peaking.  
75Ω  
2.2µF  
Plug-in prototype boards and wire-wrap boards will not  
function well. A clean layout using RF techniques is  
essential—there are no shortcuts.  
470nF  
–5V  
FIGURE 3. Impedance Converter.  
®
10  
BUF600, 601  
1...78910111213...16

中文翻译

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