BU4927G-TR

更新时间： 2025-07-19 13:00:35

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
9页	260K
描述
Power Supply Support Circuit, Fixed, 1 Channel, +2.7VV, CMOS, PDSO5, SSOP-5

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BU4927G-TR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	LSSOP, TSOP5/6,.11,37	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	0.77	其他特性：	DETECTION THRESHOLD VOLTAGE IS 2.7V
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G5	长度：	2.9 mm
湿度敏感等级：	1	信道数量：	1
功能数量：	1	端子数量：	5
最高工作温度：	125 °C	最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LSSOP
封装等效代码：	TSOP5/6,.11,37	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	1.25 mm	子类别：	Power Management Circuits
标称供电电压 (Vsup)：	2.4 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.95 mm
端子位置：	DUAL	阈值电压标称：	+2.7V
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	1.6 mm
Base Number Matches：	1

BU4927G-TR 数据手册

Technical Note

BU48□□G, BU48□□F, BU48□□FVE, BU49□□G, BU49□□F, BU49□□FVE series

 Operation Notes

1 . Absolute maximum range

Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the

failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given

when a specific mode to be beyond absolute maximum ratings is considered.

2 . GND potential

GND terminal should be a lowest voltage potential every state.

Please make sure all pins that are over ground even if include transient feature.

3 . Electrical Characteristics

Be sure to check the electrical characteristics, that are one the tentative specification will be changed by temperature,

supply voltage, and external circuit.

4 . Bypass Capacitor for Noise Rejection

Please put into the to reject noise between VDD pin and GND with 1uF over and between VOUT pin and GND with 1000pF.

If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point.

5 . Short Circuit between Terminal and Soldering

Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the

IC on circuit board please is unusually cautious about the orientation and the position of the IC. When the orientation is

mistaken the IC may be destroyed.

6 . Electromagnetic Field

Mal-function may happen when the device is used in the strong electromagnetic field.

7 . The VDD line inpedance might cause oscillation because of the detection current.

8 . A VDD -GND capacitor (as close connection as possible) should be used in high VDD line impedance condition.

9 . Lower than the mininum input voltage makes the VOUT high impedance, and it must be VDD in pull up (VDD) condition.

10. Recommended value of RL Resistar is over 10kΩ (VDET=1.5V~4.8V),

over 100kΩ (VDET=0.9~1.4V).

11. This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause

unexpected operations. Application values in these conditions should be selected carefully. If 10MΩ leakage is assumed

between the CT terminal and the GND terminal, 1MΩ connection between the CT terminal and the VDD terminal would be

recommended. Also, if the leakage is assumed between the VOUT terminal and the GND terminal, the pull up resistor

should be less than 1/10 of the assumed leak resistance.

12. External parameters

For RL, the recommended range is 10kΩ~1MΩ. There are many factors (board layout, etc) that can affect characteristics.

Please verify and confirm using practical applications.

13. Power on reset operation

Please note that the power on reset output varies with the Vcc rise up time. Please verify the actual operation.

14. Precautions for board inspection

Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be

certain to use proper discharge procedure before each process of the test operation.

To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any

equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer

and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is

OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup.

15. When the power supply, is turned on because of incertain cases, momentary Rash-current flow into the IC at the logic

unsettled, the couple capacitance, GND pattern of width and leading line must be considered.

www.rohm.com

2009.06 - Rev.C

7/8

1...4 5 678 9

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