BU4927G-TR

更新时间： 2025-07-19 13:00:35

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
9页	260K
描述
Power Supply Support Circuit, Fixed, 1 Channel, +2.7VV, CMOS, PDSO5, SSOP-5

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BU4927G-TR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	LSSOP, TSOP5/6,.11,37	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	0.77	其他特性：	DETECTION THRESHOLD VOLTAGE IS 2.7V
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G5	长度：	2.9 mm
湿度敏感等级：	1	信道数量：	1
功能数量：	1	端子数量：	5
最高工作温度：	125 °C	最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LSSOP
封装等效代码：	TSOP5/6,.11,37	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	1.25 mm	子类别：	Power Management Circuits
标称供电电压 (Vsup)：	2.4 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.95 mm
端子位置：	DUAL	阈值电压标称：	+2.7V
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	1.6 mm
Base Number Matches：	1

BU4927G-TR 数据手册

Technical Note

BU48□□G, BU48□□F, BU48□□FVE, BU49□□G, BU49□□F, BU49□□FVE series

 Reference Data

Examples of Output rising value(TPLH)and Output falling value(TPHL)

Part Number

BU4845G/F/FVE

BU4945G/F/FVE

TPLH[µs]

23.3

TPHL[µs]

275.9

3.5

354.3

VDD=4.3V5.1V

VDD=5.1V4.3V

* This data is for reference only.

This figure will vary with the application, so please confirm actual operation conditions before use.

 Explanation of Operation

For both the open drain type(Fig.12)and the CMOS output type(Fig.13), the detection and release voltages are

used as threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the Vout

terminal voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BU48□□G/F/FVE series uses an

open drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage

(VOUT) in this case becomes VDD or the voltage of the other power supply].

VDD

Vref

RESET

OUT

VOUT RESET

GND

Fig.12 (BU48□□ type internal block diagram)

Fig.13 (BU49□□ type internal block diagram)

 Timing Waveforms

Example:The following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output

voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in

Fig.12 and 13).

When the power supply is turned on, the output is unsettled

from after over the operating limit voltage (VOPL) until TPHL.

Therefore it is possible that the reset signal is not outputted

when the rise time of VDD is faster than TPHL.

V^DET+ΔV^DET

⑤

V^DET

When VDD is greater than VOPL but less than the reset release

V^OPL

voltage (VDET + VDET), output (VOUT) voltages will switch to L.

If VDD exceeds the reset release voltage (VDET + VDET), then

OUT

VOUT switches from L to H (with a delay of TPLH).

V^OH

If VDD drops below the detection voltage (VDET) when the

T^PLH

T^PHL

PLH

power supply is powered down or when there is a power supply

fluctuation, VOUT switches to L (with a delay of TPHL).

T^PHL

V^OL

The potential deference between the detection voltage and

①

②

③

④

the release voltage is known as the hysteresis width (VDET). The

system is designed such that the output does not flip-flop with

power supply fluctuations within this hysteresis width, preventing

malfunctions due to noise.

Fig.14

www.rohm.com

2009.06 - Rev.C

5/8

1 2 3 456 7 8 9

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