2/4
○ Recommended operating conditions
Parameter
Power supply voltage 1
(DAC)
Power supply voltage 2
(ADC)
Power supply voltage 3
(I2C-1)
Power supply voltage 4
(I2C-2)
Power supply voltage 5
(SD-CARD)
Power supply voltage 6
(CAMERA)
Power supply voltage 7
(Other IO)
Symbol
Min
Typ
Max
3.60
Unit
V
Parameter
Input voltage range
(ADC)
Input voltage range
(I2C-1)
Input voltage range
(I2C-2)
Input voltage range
(SD-CARD)
Input voltage range
(CAMERA)
Input voltage range
(Other IO)
Output "H" Current
*1
Output "L Current
*1
Operating temperature
range
Symbol
VIN1
Min Typ
Max
ADVDD
+0.3
I1VDD
+0.3
I2VDD
+0.3
Unit
V
DAVDD 3.00
ADVDD 3.00
3.30
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-13
-
-
-
-
-
-
-
-
-
-
3.30
3.30
3.30
3.30
2.85
3.30
1.50
3.60
3.60
3.60
3.60
3.30
3.60
1.55
V
V
V
V
V
V
V
VIN2
VIN3
VIN4
VIN5
VIN6
IOH
V
V
I1VDD
I2VDD
2.40
2.40
SDI1
V
VDD+0.3
CAVDD
+0.3
IOVDD
+0.3
SDVDD 2.70
CAVDD 2.30
IOVDD 1.70
V
V
-
mA
mA
ºC
Power supply voltage 8
(Digital CORE)
DVDD
1.45
IOL
13
85
Topr
-40
*1 Sum of absolute current of IOs in IOVDD system must be less than 100mA, and every sum of absolute current of IOs in CAVDD,
SDVDD, I1VDD and I2VDD system must be less than 26mA.
* Please supply power source in order of CORE(DVDD) → IO(IOVDD,CAVDD,SDVDD,I1VDD,I2VDD,ADVDD,DAVDD)
* Please keep RESETB terminal is LOW, until power supply is stable.
○ Electric characteristics
(Unless otherwise specified, DVDD=1.50V, DAVDD=ADVDD=I1VDD=I2VDD=SDVDD=IOVDD=3.30V, CAVDD=2.85V,
DAVSS=ADVSS=DVSS=0.0V, Ta=25ºC, fXIN=13.5MHz, fAXIN=16.384MHz, fSYS=41.0MHz(Internal Clock with PLL)
IOPWR is a generic name of I1VDD,I2VDD,SDVDD,CAVDD,IOVDD.)
Specification
Parameter
Symbol
Unit
Conditions
Min
Max
Common
Input frequency 1
fXIN
fAXIN
fSYS
5.0
30.0
32.768
41.0
MHz XIN (Duty 50±10%), When PLL is ON.
MHz AXIN(Duty 50±10%)
Input frequency 2
8.284
Internal clock frequency 1
Internal clock frequency 2
Static consumption current
Logic Block
-
-
-
MHz When PLL is ON, Except I2S Audio Block
MHz I2S Audio Block
fAUD
IDDST
32.768
200
μA When all clock stop
Input "H" Leakcurrent
Input "L" Leak current
Input Pull down "H" current 1
Input Pull down "H" current 2
Input Pull down "L" current
Input ”H” voltage 1
IIHL
IIHL
-10
10
10
μA VIH=IOPWR
-10
μA VIL=0V
IIHPD1
IIHPD2
IILPD
VIH1
25
25
100
μA Pull down pin, VIH=IOVDD
μA Pull down pin, VIH=CAVDD
μA Pull down pin, VIL=0V
100
-10
10
IOPWR×0.8
-0.3
IOPWR+0.3
IOPWR×0.2
IOPWR+0.3
IOPWR×0.15
IOPWR
0.4
V
V
V
V
V
V
V
V
Normal Input
Normal Input
Input ”L” voltage 1
VIL1
Input ”H” voltage 2
VIH2
IOPWR×0.85
-0.3
Hysteresis input pin
(TIM_TRIG,NTRST,RESETB,BIT_SEL,TCM_SEL,AUTO_READ)
Input ”L” voltage 12
Output ”H” voltage 1
Output ”L” voltage 1
Output ”H” voltage 2
Output ”L” voltage 2
DACBlock
VIL2
VOH1
VOL1
VOH2
VOL2
IOPWR-0.4
0.0
IOH=-2.0mA(DC), Output except SD_CLK, When CAVDD=3.3V
IOL=2.0mA(DC), Output except SD_CLK, When CAVDD=3.3V.
IOH=-4.0mA(DC)、SD_CLK
IOPWR-0.4
0.0
IOPWR
0.4
IOL=4.0mA(DC)、SD_CLK
DAC Bit Width
RES_DA
IDDDA
-
10
42
bits
DAC Operating current
DAC Static consumption current
Integral Non-linearity
Differential Non-linearity
Full scale voltage
32
-
mA RL=37.5Ω、RIREF=2.4kΩ、DAVDD Pin current
uA RL=37.5Ω、RIREF=2.4kΩ、DAVDD Pin current
LSB RL=37.5Ω、RIREF=2.4kΩ
IDDSTDA
INL_DA
DNL_DA
VFS_DA
5
-8.0
-2.0
1.1
+8.0
+2.0
1.4
LSB RL=37.5Ω、RIREF=2.4kΩ
V
RL=37.5Ω、RIREF=2.4kΩ
ADCBlock
ADC Bit Width
RES_AD
-
8
bits
V
Input voltage range(Upper Limit) VIN_AD_T ADVDD×0.85 ADVDD×0.95
Input voltage range(Lower Limit) VIN_AD_B ADVDD×0.05 ADVDD×0.15
V
Integral Non-linearity
INL_AD
DNL_AD
fADC
-2.0
-2.0
4.0
+2.0
+2.0
16.0
LSB
LSB
MHz
Differential Non-linearity
Change Standard clock cycle
Sample per second
Need 130*ADC_CLK for conversion by sweeping
Change cycle
fsps
30.8K
123K
sps
REV. C