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BU-61688/89

更新时间： 2024-11-14 23:36:11
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其他 - ETC /
页数 文件大小 规格书
12页 144K
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MIL-STD-1553 Components |Mini-ACE?

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BU-61688/89 数据手册

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BU-65178 /65179*/61588 /61688*/61689*  
MINIATURE ADVANCED COMMUNICATION ENGINE  
(MINI-ACE) and MINI-ACE PLUS*  
FEATURES  
DESCRIPTION  
5 Volt Only  
•
The BU-61588 Mini-ACE and The memory management scheme for  
BU-61688 Mini-ACE Plus* integrates RT mode provides three data struc-  
two 5-volt-only transceivers, protocol, tures for buffering data. These struc-  
memory management, processor tures, combined with the Mini-ACE’s  
interface logic, and 4K x 16, or 64K x extensive interrupt capability, serve to  
16* words of RAM in a choice of pin ensure data consistency while off-  
grid array (PGA), quad flat pack or gull loading the host processor.  
lead packages. The Mini-ACE is pack-  
Fully Integrated  
MIL-STD-1553 A/B  
STANAG 3838 Compliant Terminals  
•
One-Square-Inch Package  
•
•
•
Smallest BC/RT/MT In The Industry  
Hardware and Software Compatible  
with BU-61580 ACE Series  
aged in a 1.0 square inch, low profile, The Mini-ACE Plus* can optionally  
cofired ceramic multi-chip-module boot-up as a RT with the Busy bit set  
(MCM) package making it the smallest for 1760 applications.  
Flexible Processor/Memory Interface  
Bootable RT* Option  
•
•
•
•
•
•
•
•
integrated MIL-STD-1553 BC/RT/MT  
in the industry.  
The Mini-ACE BC mode implements  
several features aimed at providing an  
4K x 16 or 64K x 16* Shared RAM  
Automatic BC Retries  
The Mini-ACE provides full compatibil- efficient real-time software interface to  
ity to DDC’s BU-61580 and BU-65170 the host processor including automatic  
Advanced Communication Engine retries, programmable intermessage  
(ACE). As such, the Mini-ACE includes gap times, automatic frame repetition,  
all the hardware and software archi- and flexible interrupt generation.  
tectural features of the ACE.  
Programmable BC Gap Times  
Programmable Illegalization  
Simultaneous RT/Monitor Mode  
Operates From 10*/12 /16 / 20* MHz Clock  
The advanced architectural features of  
The Mini-ACE contains internal the Mini-ACE, combined with its small  
address latches and bidirectional data size and high reliability, make it an ideal  
buffers to provide a direct interface to choice for demanding military and indus-  
a host processor bus.  
trial processor-to-1553 applications.  
4K X 16  
OR  
TX/RX_A  
64K X 16  
*
SHARED  
RAM  
TRANSCEIVER  
A
CH. A  
DATA  
BUFFERS  
PROCESSOR  
D15-D0  
DATA BUS  
DATA BUS  
TX/RX_A  
TX/RX_B  
DUAL  
ENCODER/DECODER,  
MULTIPROTOCOL  
AND  
MEMORY  
MANAGEMENT  
ADDRESS  
BUFFERS  
PROCESSOR  
ADDRESS BUS  
ADDRESS BUS  
A15-A0  
TRANSCEIVER  
B
CH. B  
TX/RX_B  
TRANSPARENT/BUFFERED, STRBD, SELECT,  
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,  
MSB/LSB/DTGRT  
PROCESSOR  
AND  
MEMORY  
INTERFACE  
LOGIC  
PROCESSOR  
AND  
MEMORY  
CONTROL  
RT ADDRESS  
RT_AD_LAT  
RTAD4-RTAD0, RTADP  
IOEN, READYD  
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,  
8/16-BIT/DTREQ, POLARITY_SEL/DTACK  
INT  
INTERRUPT  
REQUEST  
CLK_IN,  
MSTCLR,SSFLAG/EXT_TRG  
MISCELLANEOUS  
FIGURE 1. BU-65178 / 65179* /61588 /61688*/61689* BLOCK DIAGRAM  
1996, 1999 Data Device Corporation  
©
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