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BS62LV1024STI PDF预览

BS62LV1024STI

更新时间: 2024-11-22 22:39:39
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
11页 384K
描述
Very Low Power/Voltage CMOS SRAM 128K X 8 bit

BS62LV1024STI 数据手册

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Very Low Power/Voltage CMOS SRAM  
128K X 8 bit  
BSI  
BS62LV1024  
„ DESCRIPTION  
„ FEATURES  
• Wide Vcc operation voltage : 2.4V ~ 5.5V  
• Very low power consumption :  
The BS62LV1024 is a high performance, very low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.02uA and maximum access time of 70ns in 3V operation.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
Vcc = 3.0V C-grade : 20mA (Max.) operating current  
I- grade : 25mA (Max.) operating current  
0.02uA (Typ.) CMOS standby current  
Vcc = 5.0V C-grade : 35mA (Max.) operating current  
I- grade : 40mA (Max.) operating current  
0.4uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
70ns (Max.) at Vcc = 3.0V  
The BS62LV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS62LV1024 is available in DICE form, JEDEC standard 32 pin  
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4mm  
STSOP and 8mmx20mm TSOP.  
• Data retention supply voltage as low as 1.5V  
„EPasRyOexDpaUnCsiTonFwAithMCILE2Y, CE1, and OE options  
P O W E R D IS SIPATIO N  
S P E E D  
P R O D U C T  
FAM ILY  
O P E R ATIN G  
V cc  
S tandb y  
O perating  
(ns)  
P K G TY P E  
(Icc, M ax)  
TE M P E R ATU R E  
R AN G E  
(IccS B 1, M ax)  
V cc=3V  
V cc=5V  
V cc=3V V cc=5V V cc=3V  
B S 62LV 1024S C  
B S 62LV 1024TC  
B S 62LV 1024S TC  
B S 62LV 1024P C  
B S 62LV 1024JC  
B S 62LV 1024D C  
B S 62LV 1024SI  
B S 62LV 1024TI  
B S 62LV 1024S TI  
B S 62LV 1024PI  
B S 62LV 1024JI  
B S 62LV 1024D I  
S O P -32  
TS O P -32  
S TS O P -32  
P D IP -32  
S O J-32  
D IC E  
S O P -32  
TS O P -32  
S TS O P -32  
P D IP -32  
S O J-32  
D IC E  
+0O C to +70 O C 2.4V ~ 5.5V  
70  
70  
3.0uA  
1.0uA  
1.5uA  
35m A  
20m A  
-40O C to +85 O C 2.4V ~ 5.5V  
5.0uA  
40m A  
25m A  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
NC  
A16  
A14  
A12  
A7  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
A6  
A7  
3
4
A12  
5
Address  
Memory Array  
1024 x 1024  
A14  
20  
1024  
A6  
6
BS62LV1024SC  
BS62LV1024SI  
BS62LV1024PC  
BS62LV1024PI  
BS62LV1024JC  
BS62LV1024JI  
Row  
A16  
A15  
A13  
A8  
Input  
A5  
7
A9  
A4  
8
A11  
OE  
Decoder  
Buffer  
A3  
9
A2  
10  
11  
12  
13  
14  
15  
16  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A9  
A1  
A11  
A0  
DQ0  
DQ1  
DQ2  
GND  
1024  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Column I/O  
8
Input  
Buffer  
Write Driver  
Sense Amp  
8
8
Data  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A11  
A9  
OE  
128  
Column Decoder  
14  
Output  
Buffer  
2
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
3
A8  
4
A13  
WE  
CE2  
A15  
VCC  
NC  
5
6
BS62LV1024TC  
CE2  
CE1  
WE  
OE  
Vdd  
Gnd  
7
BS62LV1024STC  
BS62LV1024TI  
BS62LV1024STI  
8
Control  
Address Input Buffer  
9
10  
11  
12  
13  
14  
15  
16  
A16  
A14  
A12  
A7  
A5 A4 A3 A2 A1 A0 A10  
A6  
A1  
A5  
A2  
A4  
A3  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.2  
April 2001  
R0201-BS62LV1024  
1

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