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BS616LV1012AC70 PDF预览

BS616LV1012AC70

更新时间: 2024-11-27 03:05:23
品牌 Logo 应用领域
BSI 静态存储器内存集成电路
页数 文件大小 规格书
9页 261K
描述
Standard SRAM, 64KX16, 70ns, CMOS, PBGA48

BS616LV1012AC70 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete包装说明:FBGA, BGA48,6X8,30
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:N最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
JESD-609代码:e0内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3端子数量:48
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA48,6X8,30
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:2.5/3.3 V认证状态:Not Qualified
最大待机电流:4.5e-7 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.017 mA
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

BS616LV1012AC70 数据手册

 浏览型号BS616LV1012AC70的Datasheet PDF文件第2页浏览型号BS616LV1012AC70的Datasheet PDF文件第3页浏览型号BS616LV1012AC70的Datasheet PDF文件第4页浏览型号BS616LV1012AC70的Datasheet PDF文件第5页浏览型号BS616LV1012AC70的Datasheet PDF文件第6页浏览型号BS616LV1012AC70的Datasheet PDF文件第7页 
Very Low Power/Voltage CMOS SRAM  
64K X 16 bit  
BSI  
BS616LV1012  
„ DESCRIPTION  
„ FEATURES  
• Wide Vcc operation voltage : 2.4 ~ 3.6V  
• Very low power consumption :  
The BS616LV1012 is a high performance, very low power CMOS Static  
Random Access Memory organized as 65,536 words by 16 bits and  
operates from a wide range of 2.4V to 3.6V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 0.4uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.  
Easy memory expansion is provided by an active LOW chip  
enable(CE) and active LOW output enable(OE) and three-state output  
drivers.  
Vcc = 3.0V C-grade : 22mA (@55ns) operating current  
I- grade : 23mA (@55ns) operating current  
C-grade : 17mA (@70ns) operating current  
I- grade : 18mA (@70ns) operating current  
0.4uA (Typ.) CMOS standby current  
• High speed access time :  
-55  
-70  
55ns  
70ns  
The BS616LV1012 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS616LV1012 is available in the JEDEC standard 44-pin TSOP  
Type II and 48-pin BGA package.  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE and OE options  
• I/O Configuration x8/x16 selectable by LB and UB pin  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
STANDBY  
Operating  
(ICC, Max)  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
PKG TYPE  
(ICCSB1, Max)  
Vcc=3.0V  
55ns  
Vcc=3.0V  
70ns  
55ns:2.8~3.6V  
70ns:2.5~3.6V  
Vcc=3.0V  
1.3uA  
BS616LV1012EC  
TSOP2-44  
+0 O C to +70 O  
-40 O C to +85 O  
C
C
2.4V ~ 3.6V  
2.4V ~ 3.6V  
55/70  
55/70  
22mA  
17mA  
18mA  
BS616LV1012AC  
BS616LV1012EI  
BS616LV1012AI  
BGA-48-0608  
TSOP2-44  
2.5uA  
23mA  
BGA-48-0608  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A4  
A3  
A2  
A1  
A0  
CE  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
GND  
DQ4  
DQ5  
DQ6  
DQ7  
A5  
A6  
A7  
OE  
UB  
LB  
A8  
A13  
DQ15  
DQ14  
DQ13  
DQ12  
GND  
VCC  
DQ11  
DQ10  
DQ9  
DQ8  
NC  
A8  
A9  
A10  
A11  
NC  
Address  
A15  
18  
512  
A14  
A12  
A7  
BS616LV1012EC  
BS616LV1012EI  
Input  
Row  
Memory Array  
512 x 2048  
Buffer  
Decoder  
A6  
A5  
A4  
17  
18  
19  
20  
21  
22  
WE  
A15  
A14  
A13  
A12  
NC  
2048  
Data  
Input  
Buffer  
16  
16  
16  
Column I/O  
DQ0  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
1
2
3
4
5
6
128  
Data  
Output  
16  
A
B
C
D
E
F
LB  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
NC  
IO0  
IO2  
Buffer  
Column Decoder  
DQ15  
IO8  
CE  
14  
CE  
WE  
OE  
UB  
IO9  
IO10  
IO11  
IO12  
IO13  
NC  
A5  
A6  
IO1  
IO3  
IO4  
IO5  
WE  
A11  
Control  
Address Input Buffer  
VSS  
VCC  
IO14  
IO15  
NC  
NC  
NC  
A14  
A12  
A9  
A7  
VCC  
VSS  
IO6  
IO7  
NC  
LB  
A11 A9 A3 A2 A1  
A0 A10  
NC  
A15  
A13  
A10  
Vcc  
Gnd  
G
H
A8  
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.  
Revision 1.0  
R0201-BS616LV1012  
1
Apr.  
2004  

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