BD6637KV/KS (Unless otherwise specified Ta=25@,VCC=3V, C_VMዙD_VMዙL_VM=5VወUNREG=7.2V)
Limit
Typ.
Symbol
<CYLINDER STARTING/DETECTION/SLOPE>
Unit
Conditions
Parameter
Fig No.
Min.
Max.
DETECT terminal charge current
DETECT terminal discharge current
DETECT terminal H voltage
DETECT terminal L voltage
ISET voltage
SL1,2 charge current
SL1,2 discharge current
SL1,2 H voltage
D_IDETO
D_IDETI
D_VDETH
D_VDETL
D_VISET
D_ISLO
D_ISLI
D_VSLH
D_VSLL
2
2
1.1
0.5
0.32
16
17
2.5
0.85
5
5
10
10
1.5
0.8
0.48
28
ꢁA
ꢁA
V
V
V
ꢁA
ꢁA
V
Fig.12
Fig.12
Fig.13
Fig.13
Fig.14
Fig.15
Fig.15
Fig.16
Fig.16
1.3
0.65
0.4
22
24
2.8
1
RD_ISET=18kꢀ
RD_ISET=18kꢀ
RD_ISET=18kꢀ
31
ዉ
SL1,2 L voltage
1.15
V
SL1,2 charge and discharge
D_RSL
0.82
1.6
0.89
2
0.96
2.4
ዉ
ዉ
current ratio
SL switching EC level
< CYLINDER VS>
Voltage gain
D_VECSL
V
D_GVS
7
8
9
TIMES
V
ዉ
ዉ
IOVS=1mA,
between VCC and output
Output H voltage
0.5
0.8
D_VVSOH
ዉ
Output L voltage
VS offset voltage
<CYLINDER FGAMP>
Input offset voltage
DC bias voltage
Voltage gain 1
Voltage gain 2
In-phase input voltage range
D_VVSOL
D_VVSOFS
ዉ
0.13
0.25
0.2
0.38
V
V
IOVS=50ꢁA
DC/DC43 in use
ዉ
ዉ
0.12
D_VFGOFS
D_VFG+
D_FAV1
D_FAV2
D_VFGCM
-12
1.3
50
30
0.35
ዉ
1.5
59
36
ዉ
12
1.7
mV
V
dB
dB
V
ዉ
ዉ
ዉ
f=3kHz
f=50kHz
Fig.20
Fig.20
ዉ
ዉ
VCC-1.1
IOH=-0.2mA,
Output H voltage
D_VFGAOH
ዉ
ዉ
0.3
0.5
V
V
ዉ
ዉ
between VCC and output
Output L voltage
D_VFGAOL
0.15
0.35
IOL=1mA
<CYLINDER FGHYS>
Measure D_FGAMP at 1K
feed back resistance
D_FG hysteresis width
D_VFGHYS
ꢂ84
ꢂ110
ꢂ136
mV
Fig.24
Measure D_FGAMP at 1K
DC bias voltage
D_VFG+
1.3
1.5
0.1
1.7
0.3
V
V
ዉ
feed back resistance
Output L voltage
<CYLINDER PGAMP>
Input offset voltage
DC bias voltage
Voltage gain 1
Voltage gain 2
D_VFGSOL
IOL=1mA
Fig.21
ዉ
D_VPGOFS
D_VPG+
D_PAV1
D_PAV2
D_VPGCM
17
1.7
-12
1.3
50
30
0.35
ዉ
1.5
59
36
ዉ
mV
V
dB
dB
V
ዉ
ዉ
ዉ
f=3kHz
f=50kHz
Fig.20
Fig.20
ዉ
ዉ
In-phase input voltage range
VCC-1.1
IOH=-0.2mA,
Output H voltage
D_VPGAOH
ዉ
ዉ
0.3
0.5
V
V
ዉ
ዉ
between VCC and output
Output L voltage
<CYLINDER PGHYS>
D_PG hysteresis width
DC bias voltage
Output L voltage
<LOADING>
D_VPGAOL
0.15
0.35
IOL=1mA
D_VPGHYS
D_VPG+
D_VPGSOL
ꢂ118 ꢂ144
1.3
ዉ
ꢂ170
1.7
0.3
mV
V
V
Fig.23
ዉ
ꢀ
1.5
0.1
IOL=1mA
Fig.21
IOUT=200mA,L_REF=L_VM
Total saturation voltage of low and
high side output transistor
Fig.
17,18
Output saturation voltage
L_VSAT
ዉ
0.3
0.5
V
L_REF pin input current
Vout-L_REF offset
L_IIREF
L_VOFS
ዉ
0.3
100
2
200
ꢁA
mV
ዉ
0
Fig.19
Forward rotation control
L_VFWD
L_VBRK
L_VREV
L_VREF
ዉ
1.3
2.3
ዉ
ዉ
1.5
ዉ
0.7
1.7
ዉ
V
V
ዉ
ዉ
ዉ
ዉ
voltage range
Brake voltage range
Reverse rotation control
voltage range
V
L_REF output open voltage
ዉ
1.3
ዲ
4/16