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BD3539NUX PDF预览

BD3539NUX

更新时间: 2024-02-24 10:03:05
品牌 Logo 应用领域
罗姆 - ROHM 稳压器动态存储器双倍数据速率
页数 文件大小 规格书
12页 434K
描述
Termination Regulators for DDR-SDRAMs

BD3539NUX 数据手册

 浏览型号BD3539NUX的Datasheet PDF文件第5页浏览型号BD3539NUX的Datasheet PDF文件第6页浏览型号BD3539NUX的Datasheet PDF文件第7页浏览型号BD3539NUX的Datasheet PDF文件第9页浏览型号BD3539NUX的Datasheet PDF文件第10页浏览型号BD3539NUX的Datasheet PDF文件第11页 
Technical Note  
BD3539FVM,BD3539NUX  
Note for Use  
1.Absolute maximum ratings  
For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working  
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because  
it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute  
maximum rating, physical safety measures are requested to be taken, such as fuses, etc.  
2.GND potential  
Bring the GND terminal potential to the minimum potential in any operating condition.  
3.Thermal design  
Consider allowable loss (Pd) under actual working condition and carry out thermal design with sufficient margin provided.  
4.Terminal-to-terminal short-circuit and erroneous mounting  
When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the  
event that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that  
enters in a clearance between outputs or output and power-GND, the IC may be destroyed.  
5.Operation in strong electromagnetic field  
The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.  
6.Built-in thermal shutdown protection circuit  
The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C  
(standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD  
circuit operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD  
circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the  
IC. Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the  
activation of the circuit premised.  
7.Capacitor across output and GND  
In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND  
for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor  
smaller than 1000 μF between output and GND.  
8.Inspection by set substrate  
In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a  
fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic  
measures, provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore,  
when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig  
and be sure to turn OFF power supply to remove the jig.  
9. Inputs to IC terminals  
This device is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer  
and the N-layer of each element form a PN junction which works as:  
a diode if the electric potentials at the terminals satisfy the following relationship; GND>Terminal A>Terminal B, or  
a parasitic transistor if the electric potentials at the terminals satisfy the following relationship; Terminal B>GND Terminal A.  
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,  
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such  
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in  
activation of parasitic elements.  
Resistor  
Transistor (NPN)  
B
Pin A  
Pin B  
Pin B  
C
E
Pin A  
B
C
E
N
N
N
P+  
P+  
P+  
P+  
N
P
P
Parasitic  
element  
N
N
Parasitic  
element  
P substrate  
P substrate  
GND  
GND  
GND  
GND  
Parasitic element  
Parasitic element  
Other adjacent elements  
www.rohm.com  
© 2009 ROHM Co., Ltd. All rights reserved.  
2009.10 - Rev.A  
8/11  

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