Technical Note
BD3539FVM,BD3539NUX
●Description of operations
・VCC
In BD3539FVM/NUX, an independent power input pin is provided for an internal circuit operation of the IC. This is used
to drive the amplifier circuit of the IC, and its maximum current rating is 4mA. The power supply voltage is 2.7 to 5.5 volts.
It is recommended to connect a bypass capacitor of 1μF or so to VCC.
・VDDQ
Reference input pin for the output voltage that may be used to satisfy the JEDEC requirement for DDR3-SDRAM
(VREF=VTT = 1/2VDDQ) by dividing the voltage inside the IC with two 100kΩ voltage-divider resistors.
For BD3539FVM/NUX, care must be taken to an input noise to VDDQ pin because this IC also cuts such noise input into
half and provides it with the voltage output divided in half. Such noise may be reduced with an RC filter consisting of
such resistance and capacitance (220Ω and 2.2μF, for instance) that may not give significant effect to voltage dividing
inside the IC.
・VTT_IN
VTT_IN is a power supply input pin for VTT output. Voltage in the range between 1.0 and 5.5 volts may be supplied to
this VTT_IN terminal, but care must be taken to the current limitation due to on-resistance of the IC and the change in
allowable loss due to input/output voltage difference.
Generally, the following voltages are supplied:
・ DDR3 VTT_IN=1.5V
Higher impedance of the voltage input at VTT_IN may result in oscillation or degradation in ripple rejection, which must be
noted. To VTT_IN terminal, it is recommended to use a 10μF capacitor characterized with less change in capacitance.
But it may depend on the characteristics of the power supply input and the impedance of the pc board wiring, which must
be carefully checked before use.
・VREF
In BD3539FVM/NUX, a reference voltage output pin independent from VTT output is given to provide a reference input for
a memory controller and a DRAM. Even if EN pin turns to “Low” level, VREF output is kept unchanged, compatible with
“Self Refresh” state of DRAM. The maximum current capability of VREF is 10mA, and a suitable capacitor is needed to
stabilize the output voltage. It is recommended to use a combination of a 1.0 to 2.2μF ceramic capacitor characterized
with less change in capacitance. For an application where VREF current is low, a capacitor of lower capacitance may be
used. If VREF current is 1mA or less, it is possible to secure a phase margin with a ceramic capacitor of 1μF more or
less.
・VTTS
An independent pin provided to improve load regulation of VTT output. In case that longer wiring is needed to the load at
VTT output, connecting VTTS from the load side may improve the load regulation.
・VTT
A DDR memory termination output pin. BD3539FVM/NUX has a sink/source current capability of ±1.0A respectively.
The output voltage tracks the voltage divided in half at VDDQ pin. VTT output is turned to OFF when VCC UVLO or
thermal shutdown protector is activated with EN pin level turned to “Low”. Do not fail to connect a capacitor to VTT output
pin for a loop gain phase compensation and a reduction in output voltage variation in the event of sudden change in load.
Insufficient capacitance may cause an oscillation. High ESR (Equivalent Series Resistance) of the capacitor may result
in increase in output voltage variation in the event of sudden change in load. It is recommended to use a 10μF or so
ceramic capacitor, though it depends on ambient temperature and other conditions.
・EN
With an input of 2.3 volts or higher, the level at EN pin turns to “High” to provide VTT output. If the input is lowered to 0.8
volts or less, the level at EN pin turns to “Low” and VTT status turns to Hi-Z. But if VCC and VDDQ are established,
VREF output is maintained.
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2009.10 - Rev.A
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