Datasheet > BCM8152_06

BCM8152_06

更新时间： 2024-09-25 04:09:03

品牌	Logo	应用领域
博通 - BOARDCOM		放大器时钟
页数	文件大小	规格书
2页	105K
描述
10-GBPS TRANSCEIVER WITH 10G CLOCK, BUS SKEW, AND LIMITING AMPLIFIER

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数据手册

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BCM8152_06 数据手册

BCM8152

10-GBPS TRANSCEIVER WITH 10G CLOCK, BUS SKEW, AND LIMITING AMPLIFIER

S U M M A R Y O F B E N E F I T S

F E A T U R E S

•

10-gigabit Multisource Agreement (MSA)/XFP-compatible

Fully integrated multirate CDR, DEMUX, CMU, and MUX

1SFI-4 parallel interface (16-bit LVDS)

10-gigabit serial transmitter clock output

Limiting amplifier

Provides compliance Optical Internetworking Forum (OIF),

Telcordia^®, ITU-T, and IEEE 802.3^™ae standards

•

Reduces design cycle and time-to-market

High level of integration allows for higher port density

solutions

•

Uses the most effective silicon economy of scale for CMOS-

based devices

On-chip PLL-based clock generator

Standard CMOS fabrication process

Line and system loopback modes

Receiver and transmitter serial data polarity invert

Bit order reversal

A P P L I C A T I O N S

•

OC-192/STM-64/10-GbE/FEC transmission equipment

SONET/SDH/10-GbE/10FC/FEC optical modules

ADD/DROP multiplexers

Analog loss-of-signal output (ALOSB)

Transmit and receive lock detect

10-word FIFO with overflow alarm absorbs system clock jitter

Reference clock: 1/16 or 1/64 of the selectable data rate

Selectable receive clock and receive data squelch

Selectable loop timing mode

Digital cross-connects

ATM switch backbone

SONET/SDH/10-GbE/10FC/FEC test equipment

Terabit and edge routers

Internal phase detector and charge pump for cleanup PLL;

external VCXO required

•

Input threshold offset adjustment and phase adjustment to

optimize bit error rate and jitter tolerance margin

Power supplies: core, LVPECL, LVDS output, CML at 1.8V,

LVDS input, and CMOS I/O at 1.8 or 3.3V

Power dissipation: 1.2W typical

Functional Block Diagram

OTX

ORX

BCM8152

ORX

OTX

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