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AX1000-2BG729I

更新时间： 2024-12-01 03:36:07
品牌 Logo 应用领域
美高森美 - MICROSEMI 栅
页数 文件大小 规格书
262页 13015K
描述
Field Programmable Gate Array, 12096 CLBs, 1000000 Gates, 870MHz, 18144-Cell, CMOS, PBGA729, 1.27 MM PITCH, PLASTIC, BGA-729

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AX1000-2BG729I 数据手册

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Revision 18  
Axcelerator Family FPGAs  
– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,  
SSTL2 Class 1 and 2, SSTL3 Class 1 and 2  
– Registered I/Os  
– Hot-Swap Compliant I/Os (except PCI)  
– Programmable Slew Rate and Drive Strength on Outputs  
– Programmable Delay and Weak Pull-Up/Pull-Down Circuits  
on Inputs  
Embedded Memory:  
– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18,  
x36 Organizations Available)  
– Independent, Width-Configurable Read and Write Ports  
– Programmable Embedded FIFO Control Logic  
Segmentable Clock Resources  
Embedded Phase-Locked Loop:  
– 14-200 MHz Input Range  
– Frequency Synthesis Capabilities up to 1 GHz  
Deterministic, User-Controllable Timing  
Unique In-System Diagnostic and Debug Capability with  
Microsemi Silicon Explorer II  
Boundary-Scan Testing Compliant with IEEE Standard 1149.1  
(JTAG)  
FuseLock™ Programming Technology Protects Against  
Reverse Engineering and Design Theft  
Leading-Edge Performance  
•
•
•
•
350+ MHz System Performance  
500+ MHz Internal Performance  
High-Performance Embedded FIFOs  
700 Mb/s LVDS Capable I/Os  
Specifications  
•
•
•
•
•
•
Up to 2 Million Equivalent System Gates  
Up to 684 I/Os  
Up to 10,752 Dedicated Flip-Flops  
Up to 295 kbits Embedded SRAM/FIFO  
Manufactured on Advanced 0.15 μm CMOS Antifuse Process  
Technology, 7 Layers of Metal  
•
•
Features  
•
•
•
•
•
Single-Chip, Nonvolatile Solution  
Up to 100% Resource Utilization with 100% Pin Locking  
1.5 V Core Voltage for Low Power  
Footprint Compatible Packaging  
Flexible, Multi-Standard I/Os:  
•
•
•
•
– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation  
– Bank-Selectable I/Os – 8 Banks per Chip  
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI,  
and 3.3 V PCI-X  
– Differential I/O Standards: LVPECL and LVDS  
Table 1 • Axcelerator Family Product Profile  
Device  
AX125  
125,000  
82,000  
AX250  
250,000  
154,000  
AX500  
500,000  
286,000  
AX1000  
1,000,000  
612,000  
AX2000  
2,000,000  
1,060,000  
Capacity (in Equivalent System Gates)  
Typical Gates  
Modules  
Register (R-cells)  
Combinatorial (C-cells)  
Maximum Flip-Flops  
Embedded RAM/FIFO  
Number of Core RAM Blocks  
Total Bits of Core RAM  
Clocks (Segmentable)  
Hardwired  
672  
1,408  
2,816  
2,816  
2,688  
5,376  
5,376  
6,048  
12,096  
12,096  
10,752  
21,504  
21,504  
1,344  
1,344  
4
12  
16  
36  
64  
18,432  
55,296  
73,728  
165,888  
294,912  
4
4
8
4
4
8
4
4
8
4
4
8
4
4
8
Routed  
PLLs  
I/Os  
I/O Banks  
8
8
8
8
8
Maximum User I/Os  
Maximum LVDS Channels  
Total I/O Registers  
168  
84  
248  
124  
744  
336  
516  
684  
168  
258  
342  
504  
1,008  
1,548  
2,052  
Package  
PQ  
208  
208  
BG  
FG  
CQ  
729  
484, 676, 896  
352  
256, 324  
256, 484  
208, 352  
484, 676  
208, 352  
896, 1152  
256, 352  
624  
CG  
624  
March 2012  
i
© 2012 Microsemi Corporation  
1234567...262

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AX1000-2BGG729 MICROSEMI

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 		Field Programmable Gate Array, 12096 CLBs, 1000000 Gates, 870MHz, 18144-Cell, CMOS, PBGA72
AX1000-2BGG729I MICROSEMI

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 		Field Programmable Gate Array, 12096 CLBs, 1000000 Gates, 870MHz, 18144-Cell, CMOS, PBGA72
AX1000-2BGG729M MICROSEMI

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 		Field Programmable Gate Array, 12096 CLBs, 1000000 Gates, CMOS, PBGA729
AX1000-2BGG896 ACTEL

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 		Axcelerator Family FPGAs

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