Datasheet > AU5790D/N,112

AU5790D/N,112

更新时间： 2024-02-22 06:20:11

品牌	Logo	应用领域
恩智浦 - NXP		电信光电二极管电信集成电路
页数	文件大小	规格书
20页	115K
描述
IC DATACOM, INTERFACE CIRCUIT, PDSO8, PLASTIC, SO-8, Network Interface

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技术参数
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AU5790D/N,112 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	R-PDSO-G8
长度：	4.9 mm	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	1.75 mm	标称供电电压：	13 V
表面贴装：	YES	电信集成电路类型：	INTERFACE CIRCUIT
温度等级：	AUTOMOTIVE	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

AU5790D/N,112 数据手册

Philips Semiconductors

Product data

Single wire CAN transceiver

AU5790

Table 3 shows the maximum power dissipation of an AU5790 without tripping the thermal overload protection, for specified combinations of

package, board configuration, and ambient temperature.

Table 3. Maximum power dissipation

tot

Power Dissipation Max.

T = 85 °C T = 125 °C

Thermal Resistance

Additional Foil Area for

Heat Dissipation

Board Type

SO-8 on High

K/W

103

631

793

243

305

Normal traces

Conductance Board

225 Sq. mm of copper

foil attached to pin 8.

SO-8 on Low

Conductance Board

Normal traces

163

119

399

546

153

210

225 Sq. mm of copper

attached to pin 8.

SO-8 on Very Low

Conductance Board

Normal traces

194

135

335

481

129

185

225 Sq. mm of copper

attached to pin 8.

SO-14 on High

Conductance Board

Normal traces

1032

1300

397

500

105 Sq. mm of copper

attached to each of pins

1, 7, 8, & 14.

SO-14 on Low

Conductance Board

Normal traces

103

631

929

243

357

105 Sq. mm of copper

attached to each of pins

1, 7, 8, & 14.

SO-14 on Very Low

Conductance Board

Normal traces

126

516

793

198

305

105 Sq. mm of copper

attached to each of pins

1, 7, 8, & 14.

NOTES:

1. The High Conductance board is based on modeling done to EIA/JEDEC Standard JESD51-7. The board emulated contains two one ounce

thick copper ground planes, and top surface copper conductor traces of two ounce (0.071 mm thickness of copper).

2. The Low Conductance board is based on modeling done to EIA/JEDEC Standard EIA/JESD51-3. The board does not contain any ground

planes, and the top surface copper conductor traces of two ounce (0.071 mm thickness of copper).

3. The Very Low Conductance board is based on the EIA/JESD51-3, however the thickness of the surface conductors has been reduced to

0.035 mm (also referred to as 1.0 Ounce copper).

4. The above mentioned JEDEC specifications are available from: http://www.jedec.org/

2001 May 18

1...12 13 141516 17 18...20

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