5
4
3
2
1
J1 and J2 goes down to the mother
board.
ATTiny23U / ATTiny43U Routing&Socket card
See layout guidelines for floorplan
Keep capacitors close to IC pins
SILK: USAGE:
BOOST regulator:
open Vtarget jumper on mainboard
D
C
B
A
D
C
B
A
short J8
J1
J2
strap wire from mainboard Vtarget pin1 to J3 (Vbat) pin 1
U4
w/o BOOST regulator
short J3 (Vbat)
open J8
J1
ATtiny43U-MLF
J2
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
GND
VTG
VTG
GND
PJ0
PJ2
PJ4
PJ6
VTG
PA0
PA1
PJ1
PA0
PA2
PA4
PA6
PA1
PA3
PA5
PA7
short Vtarget jumper on mainboard
PA2
PA4
PA6
PA3
PA5
PA7
PJ3
PJ5
PJ7
C43
100n
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
PB7
PB1
PB0
PA7
PA6
PA5
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
6
7
8
9
10
20
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
GND
VTG
GND
VTG
PB7 [INT0]
VCC
GND
LSW
VBAT
PB1 [OC0A]
PB0 [TO]
PA7 [RST-dW]
PA6 [CLKI]
PA5 [AIN1]
PB0
PB1
PK0
PK2
PK4
PK6
PK1
PK3
PK5
PK7
PB0
PB2
PB4
PB6
PB1
PB3
PB5
PB7
GND
19
18
17
16
PB2
PB4
PB6
PB3
PB5
PB7
GND
R16
LSW_MLF
GND
VTG
GND
VTG
680R
PC0
PC1
PL0
PL2
PL4
PL6
PL1
PL3
PL5
PL7
PC2
PC4
PC6
PC3
PC5
PC7
C37
100n
JS3
GND
VTG
GND
VTG
PD0
PD1
PM0
PM2
PM4
PM6
PM1
PM3
PM5
PM7
GND
PD2
PD4
PD6
PD3
PD5
PD7
YMJ-02-O-BK
GND
GND
VTG
GND
VTG
PE0
PE1
PN0
PN2
PN4
PN6
PN1
PN3
PN5
PN7
PE2
PE4
PE6
PE3
PE5
PE7
Silk: J3 (Vbat)
"pin1 +" and
"pin2 -"
NOTE: When connecting external
power to J3
Silk: J8
Short J8 to connect Boost to
VCC / VTG
GND
VTG
GND
VTG
- open Vtarget on mainboard
- short J8
PF0
PF1
PP0
PP2
PP4
PP6
PP1
PP3
PP5
PP7
L1
PF2
PF4
PF6
PF3
PF5
PF7
BATS
LSW
MSS6132-153ML
C31
100p
+
C32
10u
C27
4.7u
D1
J8
GND
VTG
GND
VTG
PG0
PG1
PQ0
PQ2
PQ4
PQ6
PQ1
PQ3
PQ5
PQ7
vbus
uvcon
MBR0520L_NL
CD075014 1X2
J3
PG2
PG4
PG6
PG3
PG5
PG7
2
1
2
1
VTG
1
2
R51
2k
dp
dn
usbid
GND
C52
100p
C40
22 uF
C41
22 uF
GND
VTG
CD075014 1X2
PH0
PH1
PH2
PH4
PH6
PH3
PH5
PH7
VCC
GND
PDATA0
PDATA1
PDATA3
PDATA5
PDATA7
PCTRL1
PCTRL3
PCTRL5
GND
GND
PB0
PB2
PB4
PB6
PB1
PB3
PB5
PB7
PA5
PA0
PA1
PDATA2
PDATA4
PDATA6
PCTRL0bs2
PCTRL2oe
PCTRL4bs1
PCTRL6xa1
BOARD_ID0
GND
VTG
XTAL1
aref0
PA6
U5
XTAL2
LSW_SOIC
MOSI
rdy
wr
xa0
PB4
PB5
PB6
GND
tosc1
MISO
SCK
tdi
tdo
tms
tck
R15
PA4
PA3
PA2
11
10
9
8
7
6
5
4
3
2
1
GND
GND
LSW
VBAT
GND
VCC
PB7 [INT0]
tosc2
reset
12
13
14
15
16
17
18
19
20
pagel PCTRL7
PA7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
[ADC0] PA0
680R
C36
100n
C42
100n
BOARD_ID1
GND
[ADC1] PA1 PB6 [USCK-SCL]
[ADC2] PA2
[ADC3] PA3
[AIN0] PA4
[AIN1] PA5
[CLKI] PA6
[RST-dW] PA7
PB5 [DO-OC1B]
PB4 [DI-OC1A]
PB3 [T1-CLKO]
PB2 [OC0B]
BOARD_ID4
BOARD_ID5
VCC
VCC
GND
Mating FSI-150
GND
Mating FSI-150
U1
PB1 [OC0A]
PB0 [TO]
ID: 0x09
3
1
6
I0
I1
I2
4
ATtiny43U-SOIC
Y
a: 0
b: /(A XOR B)
ev A XNOR B
ISP
J11
NC7SZ57P6X
GND
1
3
5
2
4
6
MISO
SCK
RESET GND
VCC
MOSI
CD075014 2X3
SOCKET_RESET
VCC
ST1
PROG DATA
PROG CTRL
C22
100n
J10
1
2
3
20
19
PB0 [TO]
PB1 [OC0A]
PB2 [OC0B]
[RST-dW] PA7
1
2
4
6
8
[CLKI] PA6
[AIN1] PA5
[AIN0] PA4
[ADC3] PA3
[ADC2] PA2
GND
18
17
16
15
14
13
12
11
3
5
7
9
J9
PCB1
4
PB3 [T1-CLKO]
PB4 [DI-OC1A]
PB5 [DO-OC1B]
1
2
4
6
8
5
6
7
3
5
7
9
10
PB6 [USCK-SCL] [ADC1] PA1
CD075014 2X5
8
9
10
PB7 [INT0]
VCC
GND
[ADC0] PA0
VBAT
10
LSW
CD075014 2X5
E3
E4
652D0202211-001
GND
A08-0409.C
C44
100n
GND
GND
PCB Clip Hole, STK600 RoutinPgCcBaCrdlip Hole, STK600 Routing card
ATMEL Norway AS
Vestre Rosten 79
N-7075 TILLER
Norway
AUX
J12
E7
E5
E6
E1
E2
1
3
5
7
9
2
4
6
8
Be aware of conflicting components
on STK600 while placing J12 !
XTAL1
SOCKET_RESET
GND
Title
GND
GND
STK600 socket card ATTiny23V / ATTiny43V
GND
VCC
Size Document Number
Rev
PC2
10
FIDUCIAL
FIDUCIAL
FIDUCIAL
GND
A3
<Doc>
PCB Clip Hole, STK600 RoutinPgCcBaCrdlip Hole, STK600 Routing card
CD075014 2X5
Date:
Wednesday, March 05, 2008
Sheet
1
of
1
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