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ATR28XXS_07 PDF预览

ATR28XXS_07

更新时间: 2022-05-13 05:16:52
品牌 Logo 应用领域
英飞凌 - INFINEON 转换器
页数 文件大小 规格书
12页 163K
描述
HYBRID-HIGH RELIABILITY DC/DC CONVERTER

ATR28XXS_07 数据手册

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ATR28XXS Series  
ATR2805S  
Table II. Electrical performance Characteristics - continued  
Symbol  
Conditions  
-55 C TC +125 C  
Group A  
Device  
Types  
Limits  
Units  
Subgroups  
°
°
V
= 28VDC 5%, C = 0  
±
L
IN  
Min Max  
Unless otherwise specified  
Recovery time transient step  
line changes 5, 8, 9  
TTLINE  
Input step 16V to/from  
40VDC, IOUT = 6000mA  
4,5,6  
01  
10  
ms  
Turn on overshoot  
VTonOS  
TonD  
TrLF  
IOUT =0 and 6000mA  
IOUT =0 and 6000mA  
4,5,6  
4,5,6  
4,5,6  
01  
01  
01  
500  
25  
25  
mV pk  
ms  
ms  
Turn on delay 10  
Load fault recovery 5, 10  
Notes to Specifications  
1
2
3
4
Parameter guaranteed by line and load regulation tests.  
Bandwidth guaranteed by design. Tested for 20KHz to 2.0MHz.  
Output voltage measured at load with remote sense leads connected across load.  
Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess of  
the maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing  
as a short circuit during turn on.  
5
6
Parameter shall be tested as part of design characterization and after design or process changes. There after parameters shall be  
guaranteed to the limits specified in table II.  
An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit  
protection and is the condition of maximum power dissipation.  
7
8
9
Load step transition time between 2.0µs and 10µs.  
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1.0% of VOUT at 50% load.  
Input step transition time between 2.0µs and 10µs.  
10 Turn on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the  
inhibit pin (pin 2) while power is applied to the input.  
www.irf.com  
5

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