Datasheet > ATF633S21T

ATF633S21T

更新时间： 2024-02-24 22:50:39

品牌	Logo	应用领域
POSEICO		开关
页数	文件大小	规格书
3页	81K
描述
FAST SWITCHING THYRISTOR

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中文翻译

获取价格

数据手册

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ATF633S21T 数据手册

POSEICO SPA

Via N. Lorenzi 8, 16152 Genova - ITALY

Tel. +39 010 6556234 - Fax +39 010 6557519

Sales Office:

POSEICO

POSEICO SPA

POwer SEmiconductors Italian COrporation

Tel. +39 010 6556775 - Fax +39 010 6445141

FAST SWITCHING THYRISTOR

ATF633

Repetitive voltage up to

Mean on-state current

Surge current

2100 V

1390 A

17 kA

FINAL SPECIFICATION

Turn-off time

60 µs

mag 06 - ISSUE : 3

Symbol

Characteristic

Conditions

Value

Unit

[°C]

BLOCKING

V RRM

V RSM

V DRM

I RRM

I DRM

Repetitive peak reverse voltage

Non-repetitive peak reverse voltage

Repetitive peak off-state voltage

Repetitive peak reverse current

Repetitive peak off-state current

125

2100

2000

2100

100

V=VRRM

V=VDRM

100

CONDUCTING

I T (AV)

I TSM

I² t

Mean on-state current

Surge on-state current, non repetitive

I² t

180°sin, 50 Hz, Th=55°C, double side cooled

180°sin, 1 kHz, Th=55°C, double side cooled

sine wave, 10 ms

1390

1345

125

without reverse voltage

1445 x1E3

1,94

A²s

V T

On-state voltage

On-state current =

2000 A

V T(TO)

r T

Threshold voltage

125

1,30

On-state slope resistance

125 0,320

mohm

SWITCHING

di/dt

dv/dt

Critical rate of rise of on-state current, min

Critical rate of rise of off-state voltage, min

Gate controlled delay time, typical

From 75% VDRM up to 1200 A, gate 10V 5 ohm

Linear ramp up to 75% of VDRM

125

400

600

0,8

A/µs

V/µs

µs

VD=200V, gate source 20V, 10 ohm , tr=.5 µs

Circuit commutated turn-off time

di/dt = 60

dV/dt = 200 V/µs , up to 80% VDRM

di/dt = 60 A/µs, I I = 1000

VR = 50

A/µs, I I = 1000

125

µs

Q rr

I rr

I H

Reverse recovery charge

Peak reverse recovery current

Holding current, typical

125

450

195

µC

VD=5V, gate open circuit

VD=12V, tp=30µs

I L

Latching current, typical

GATE

V GT

I GT

Gate trigger voltage

VD=5V

125

3,5

350

0,25

Gate trigger current

VD=5V

V GD

V FGM

Non-trigger gate voltage, min.

Peak gate voltage (forward)

Peak gate current

VD=VDRM

FGM

V RGM

P GM

Peak gate voltage (reverse)

Peak gate power dissipation

Average gate power dissipation

Pulse width 100 µs

150

P G(AV)

MOUNTING

R th(j-h)

T j

Thermal impedance, DC

Operating junction temperature

Mounting force

Junction to heatsink, double side cooled

°C/kW

°C

-30 / 125

17.0 / 21.0

520

Mass

tq code

D 10 µs C 12 µs B 15 µs A 20 µs L 25 µs

M 30 µs N 35 µs P 40 µs R 45 µs S 50 µs

T 60 µs U 70 µs W 80 µs X 100µs Y 150µs

tq code

ORDERING INFORMATION : ATF633 S 21 T

VDRM&VRRM/100

standard specification

12 3

中文翻译

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