Datasheet > ATF22V10CQZ

ATF22V10CQZ

更新时间： 2024-11-23 22:07:11

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
13页	276K
描述
Highperformance EE PLD

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中文翻译

获取价格

数据手册

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ATF22V10CQZ 数据手册

Features

• Industry-standard Architecture

• 12 ns Maximum Pin-to-pin Delay

• Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)

• CMOS and TTL Compatible Inputs and Outputs

• Advanced Electrically-erasableTechnology

– Reprogrammable

– 100% Tested

• Latch Feature Holds Inputs to Previous Logic State

• High-reliability CMOS Process

– 20 Year Data Retention

– 100 Erase/Write Cycles

– 2,000V ESD Protection

High-

performance

EE PLD

– 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Standard Pinouts

• PCI Compliant

Block Diagram

ATF22V10CZ

ATF22V10CQZ

Description

The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)

programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable

(continued)

Pin Configurations

All Pinouts Top View

TSSOP

CLK/IN

VCC

I/O

Pin Name Function

CLK

Clock

Logic Inputs

Bi-directional Buffers

+5V Supply

I/O

VCC

PLCC

GND

DIP/SOIC

25 I/O

24 I/O

23 I/O

22 GND*

21 I/O

20 I/O

19 I/O

CLK/IN

24 VCC

23 I/O

22 I/O

21 I/O

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 IN

GND*

IN 10

IN 11

Rev. 0778H–03/01

IN 10

IN 11

Note:

For PLCC, P1, P8, P15 and P22 can be left

unconnected. For superior performance, con-

nect VCC to pin 1 and GND to 8, 15, and 22.

GND 12

12 3 4 5 6 7...13

中文翻译

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