Datasheet > ATF22V10C(Q)

ATF22V10C(Q)

更新时间： 2024-11-30 23:33:07

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件
页数	文件大小	规格书
18页	335K
描述
ATF22V10C(Q) [Updated 1/02. 18 Pages] 500 gate high-speed electrically erasable PLD. 24 pins

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数据手册

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ATF22V10C(Q) 数据手册

Features

• Industry-standard Architecture

– Low-cost, Easy-to-use Software Tools

• High-speed, Electrically Erasable Programmable Logic Devices

– 5 ns Maximum Pin-to-pin Delay

• CMOS- and TTL-compatible Inputs and Outputs

– Latch Feature Holds Inputs to Previous Logic States

• Pin-controlled Standby Power (10 µA Typical)

• Advanced Flash Technology

– Reprogrammable

– 100% Tested

• High-reliability CMOS Process

High-

– 20-year Data Retention

– 100 Erase/Write Cycles

– 2,000V ESD Protection

– 200 mA Latch-up Immunity

performance

EE PLD

• Dual Inline and Surface Mount Packages in Standard Pinouts

• PCI-compliant

• True Input Transition Detection “Z” and “QZ” Version

ATF22V10C

ATF22V10CQ

See separate datasheet

for ATF22V10CZ and

ATF22V10CQZ options.

Pin Configurations

TSSOP

All Pinouts Top View

CLK/IN

VCC

I/O

Pin Name Function

IN/PD

CLK

Clock

Logic Inputs

Bi-directional Buffers

Ground

I/O

GND

VCC

GND

+5V Supply

Power-down

PLCC

DIP/SOIC

CLK/IN

24 VCC

23 I/O

22 I/O

21 I/O

20 I/O

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 IN

IN/PD

25 I/O

24 I/O

23 I/O

22 GND*

21 I/O

20 I/O

19 I/O

IN/PD

GND*

IN 10

IN 11

IN 10

IN 11

GND 12

Note:

For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be

left unconnected. However, if they are connected, supe-

rior performance will be achieved.

Rev. 0735P–PLD–01/02

12 3 4 5 6 7...18

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